Abstract: Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. Wordline trunk regions extend across the array and along a third direction substantially orthogonal to the second direction of the columns. Wordline branch regions extend from the wordline trunk regions and along the first direction. Semiconductor-material fins are along the rows. Each semiconductor-material fin has a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. Each channel region is overlapped by a wordline branch. Digit lines extend along the columns and are electrically coupled with the second source/drain regions. Charge-storage devices are electrically coupled with the first source/drain regions.

Abstract: In some embodiments, a method used in forming an array of memory cells comprises uses no more than two photolithographic masking steps are used in forming both: (a) sense lines longitudinally extending in a column direction that are individually directly above and electrically coupled to the upper source/drain regions of multiple of the second pedestals in the column direction; and (b) spaced elevationally-extending vias laterally between immediately-adjacent of the sense lines directly above and electrically coupled to the upper source/drain regions of multiple of the first pedestals. Other embodiments are disclosed.

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one another by a first pitch. Protective knobs are formed over the conductive lines and are arranged in rows. The protective knobs within each row are spaced along a second pitch which is greater than the first pitch. The protective knobs protect regions of the conductive lines while leaving other regions of the conductive lines unprotected. The unprotected regions are recessed so that the protected regions become tall regions and the unprotected regions become short regions. The protective knobs are removed. Conductive structures are formed over the conductive lines. The conductive structures are spaced along the second pitch. Each of the conductive lines is uniquely coupled to only one of the conductive structures. Some embodiments include integrated assemblies.

Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one another by a first pitch. Protective knobs are formed over the conductive lines and are arranged in rows. The protective knobs within each row are spaced along a second pitch which is greater than the first pitch. The protective knobs protect regions of the conductive lines while leaving other regions of the conductive lines unprotected. The unprotected regions are recessed so that the protected regions become tall regions and the unprotected regions become short regions. The protective knobs are removed. Conductive structures are formed over the conductive lines. The conductive structures are spaced along the second pitch. Each of the conductive lines is uniquely coupled to only one of the conductive structures. Some embodiments include integrated assemblies.

Abstract: In some embodiments, memory circuitry comprises a pair of immediately-adjacent memory arrays having space laterally there-between. The memory arrays individually comprise memory cells individually having upper and lower elevationally-extending transistors and a capacitor elevationally there-between. The memory arrays comprise individual rows that (a) have an upper access line above and directly electrically coupled to a lower access line, and (b) are directly electrically coupled to one another across the space. The lower access line in one of the rows extends across the space from one of the memory arrays to the other of the memory arrays. Another of the rows comprises a conductive interconnect extending across a portion of the space. The conductive interconnect includes a horizontally-extending portion within the space that is laterally offset from the another row. Other aspects and implementations are disclosed.

Abstract: Electronic apparatus, systems, and methods in a variety of applications can include a fin field effect transistor (FinFET) having a deposited fin body. Such a FinFET can be implemented as an access transistor in a circuit of an integrated circuit. In an embodiment, an array of FinFETs having a deposited fin bodies can be disposed on digitlines. For the array of FinFETs having a deposited fin bodies structured in memory cells of a memory, the digitlines can be coupled to sense amplifiers. Additional apparatus, systems, and methods are disclosed.

Abstract: Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.

Abstract: Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include a memory array having rows of fins. Each fin has at least one channel region. Each channel region extends from a first source/drain region to a second source/drain region. The channel regions within each row of fins include first channel regions and second channel regions. Wordline configurations extend along the rows of fins. Each wordline configuration has a first wordline component operated in tandem with a second wordline component. The first wordline components electrically couple with only the first channel regions and the second wordline components electrically couple with only the second channel regions.

Abstract: Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.

Abstract: Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.

Abstract: Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trough between the first and second pedestals. Digit lines are electrically coupled with the first source/drain regions. Ferroelectric capacitors are electrically coupled with the second source/drain regions. Wordlines are along the rows of fins and overlap the channel regions. Conductive isolation lines are under the wordlines along the rows of fins.

Abstract: Some embodiments include a memory array having rows of fins. Each fin has at least one channel region. Each channel region extends from a first source/drain region to a second source/drain region. The channel regions within each row of fins include first channel regions and second channel regions. Wordline configurations extend along the rows of fins. Each wordline configuration has a first wordline component operated in tandem with a second wordline component. The first wordline components electrically couple with only the first channel regions and the second wordline components electrically couple with only the second channel regions.

Abstract: Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. Wordline trunk regions extend across the array and along a third direction substantially orthogonal to the second direction of the columns. Wordline branch regions extend from the wordline trunk regions and along the first direction. Semiconductor-material fins are along the rows. Each semiconductor-material fin has a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. Each channel region is overlapped by a wordline branch. Digit lines extend along the columns and are electrically coupled with the second source/drain regions. Charge-storage devices are electrically coupled with the first source/drain regions.

Abstract: Some embodiments include a memory array having rows of fins. Each fin has at least one channel region. Each channel region extends from a first source/drain region to a second source/drain region. The channel regions within each row of fins include first channel regions and second channel regions. Wordline configurations extend along the rows of fins. Each wordline configuration has a first wordline component operated in tandem with a second wordline component. The first wordline components electrically couple with only the first channel regions and the second wordline components electrically couple with only the second channel regions.

Abstract: Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first source/drain region extends to a first height. The second source/drain region extends to a second height less than the first height. The channel region extends along a trough between the first and second source/drain regions. A charge-storage device is over the first source/drain region. A first sense/access line is along a sidewall of the fin and is spaced from the channel region by dielectric material. A second sense/access line is over the second source/drain region. An uppermost surface of the second sense/access line is beneath an uppermost surface of the first source/drain region. Some embodiments include memory arrays, and some embodiments include methods of forming memory arrays.

Abstract: Some embodiments include a floating body transistor which has a gate structure configured as a bracket having two upwardly-projecting sidewalls joined to a base. A region between the upwardly-projecting sidewalls is an interior region of the bracket. The interior region of the bracket has an interior surface along an upper surface of the base, and along inward surfaces of the upwardly-projecting sidewalls. The sidewalls are a first sidewall and a second sidewall. The first and second sidewalls have first and second notches, respectively, which extend downwardly into the first and second sidewalls. The first and second notches are horizontally aligned with one another. Dielectric material lines the interior surface of the bracket. A semiconductor material body is within the interior region of the bracket and along the dielectric material. The semiconductor material body has a third notch which is horizontally aligned with the first and second notches.

Abstract: Some embodiments include memory arrays having rows of fins. Each fin includes a first pedestal, a second pedestal and a trench between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trench between the first and second pedestals. The rows are subdivided amongst deep-type (D) rows and shallow-type (S) rows, with the deep-type rows having deeper channel regions than the shallow-type rows. Some embodiments include rows of fins in which the channel regions along individual rows are subdivided amongst deep-type (D) channel regions and shallow-type (S) channel regions, with the deep-type channel regions being below the shallow-type channel regions.