Patents by Inventor Werner Webers

Werner Webers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6842363
    Abstract: A magnetoresistive memory includes a control circuit with a first pole that, via a reading distributor, can be individually connected to first ends of bit lines by switching elements. The control circuit also has a second pole, which supplies power to an evaluator, and has a third pole that is connected to a reference voltage source. The readout circuit additionally includes a third voltage source having a voltage, which is approximately equal to the voltage of the first reading voltage source and which can be individually connected to second ends of the bit lines by means of switching elements. Finally, the readout circuit includes a fourth voltage source, which can be individually connected to second ends of the word lines by means of switching elements.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: January 11, 2005
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Werner Weber, Hugo Van Den Berg
  • Patent number: 6833731
    Abstract: A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer period of time or/and in remote sites of use and are dependent upon a supply voltage are impaired with the dependency-related disadvantages, such as the necessity of expensive EEPROMs or significantly increased maintenance expenditure.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: December 21, 2004
    Assignee: Infineon Technologies AG
    Inventors: Christl Lauterbach, Georg Braun, Udo Ollert, Werner Weber
  • Patent number: 6822916
    Abstract: As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: November 23, 2004
    Assignee: Infineon Technologies AG
    Inventors: Alexander Frey, Werner Weber, Till Schlösser
  • Publication number: 20040213037
    Abstract: A magnetoresistive memory includes a control circuit with a first pole that, via a reading distributor, can be individually connected to first ends of bit lines by switching elements. The control circuit also has a second pole, which supplies power to an evaluator, and has a third pole that is connected to a reference voltage source. The readout circuit additionally includes a third voltage source having a voltage, which is approximately equal to the voltage of the first reading voltage source and which can be individually connected to second ends of the bit lines by means of switching elements. Finally, the readout circuit includes a fourth voltage source, which can be individually connected to second ends of the word lines by means of switching elements.
    Type: Application
    Filed: June 5, 2003
    Publication date: October 28, 2004
    Inventors: Roland Thewes, Werner Weber, Hugo Van Den Berg
  • Patent number: 6748862
    Abstract: The clamping device is used to adjust at least one register element in a printing machine. The device has an upper clamping rail, to which the register element is fixed. The upper clamping rail can be moved in a guide and fixed in position in order to adjust the register element.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: June 15, 2004
    Assignee: Heidelberger Druckmaschinen AG
    Inventors: Eckart Frankenberger, Ludwig Becker, Werner Weber
  • Publication number: 20040094349
    Abstract: A control device for a restraining system in a motor vehicle is proposed, a safety switch, which also includes a watchdog, performing the function of a safety switch in the control device. The safety switch monitors sensor signals which are transmitted to the processor of the control device for plausibility and triggers appropriate restraining means via a time unit for a predefined time period only when the safety switch itself detects a trigger event. On the basis of supplementary data from the sensor signals, the safety switch infers how the sensor signals are to be processed. The safety switch is designed such that it triggers restraining means correspondingly assigned to the sensors. When the control device is switched on, the processor performs a test of the safety switch by generating a test signal using the sensors.
    Type: Application
    Filed: December 31, 2003
    Publication date: May 20, 2004
    Inventors: Hartmut Schumacher, Peter Taufer, Torsten Grotendiek, Harald Tschentscher, Werner Weber
  • Patent number: 6717843
    Abstract: A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage cells, each storage cell having two intersecting electric conductors and a layer system comprising magnetic layers located at the intersection of the electric conductors. The memory is characterized in that the layer system is designated as a multilayer system with two or more magnetic layers, wherein at least two of the magnetic layers have a magnetization direction that can be set independently of one another. Further, the magnetization direction of the individual layers may be changed on the basis of the electric current flowing through the electric conductors.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: April 6, 2004
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Werner Weber, Siegfried Schwarzl
  • Publication number: 20040045839
    Abstract: The inventive biosensor has three electrodes, the first electrode having a retaining area for retaining probe molecules which bind with the macromolecular biopolymers. The second electrode and the third electrode are configured in such a way that the redox process is part of a redox recycling system on said second and third electrodes.
    Type: Application
    Filed: January 16, 2003
    Publication date: March 11, 2004
    Inventors: Roland Thewes, Werner Weber
  • Patent number: 6625076
    Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: September 23, 2003
    Assignee: Infineon Technologies AG
    Inventors: Werner Weber, Roland Thewes
  • Patent number: 6611614
    Abstract: Sensor elements are arranged in a hexagonal grid. A processor element in the form of a primitive automaton is assigned to each of the sensor elements in the grid. The processor elements are set up to perform algorithms which enable lines of a fingerprint to be simplified such that characteristic minutiae of the fingerprint (endings and branchings of the lines) can be extracted. The processor elements are embodied using CMOS/Neuron MOS threshold value logic or using CMOS/NMOS pass transistor logic. The image grid can be read out via read-out circuits as a matrix.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: August 26, 2003
    Assignee: Infineon Technologies AG
    Inventors: Stefan Jung, Roland Thewes, Werner Weber
  • Patent number: 6580636
    Abstract: The magnetoresistive memory has a reduced current density in the bit lines and/or word lines. This avoids electromigration problems. The current density is reduced such that a compact field concentration is attained, for example, by the use of ferrite in the area around the magnetic memory cells.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: June 17, 2003
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Werner Weber
  • Publication number: 20030081475
    Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.
    Type: Application
    Filed: December 10, 2002
    Publication date: May 1, 2003
    Applicant: Infineon Technologies AG
    Inventors: Werner Weber, Roland Thewes
  • Patent number: 6539506
    Abstract: A read/write memory includes a monolithically integrated self-test device which iteratively enables a defect test with a redundancy analysis, without significant external test aids. The test is achieved essentially by virtue of the fact that word lines to be repaired are stored and excluded from further examinations and in each case the line having the most defects not previously detected is always determined and examined first, until either the number of repair lines no longer suffices or no more defects occur. An associated test method is also provided.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: March 25, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Stefan Lammers, Werner Weber
  • Patent number: 6525978
    Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: February 25, 2003
    Assignee: Infineon Technologies AG
    Inventors: Werner Weber, Roland Thewes
  • Patent number: 6512688
    Abstract: A magneto resistive memory contains first switches, a word line voltage source generating a word line voltage connected to the first switches, a line node, second switches, and cells formed of cell resistors each having a first terminal connected to the word line voltage through one of the first switches and a second terminal connected to the line node through one of the second switches. A reference resistor is connected to the line node and a reference voltage source is connected to the reference resistor. The reference resistor with the reference voltage source brings about a reduction in a respective cell current, flowing from the line node, by an average current. A device is connected to the line node and evaluates the cell resistors. The device has an amplifier for converting a difference between the respective cell current and the average current into a voltage functioning as an evaluation signal.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: January 28, 2003
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Werner Weber
  • Patent number: 6490192
    Abstract: A magnetoresistive memory is described and contains a common word line voltage source, bit lines, word lines crossing the bit lines, and a memory cell array having memory cells with cell resistors. The memory cell array further has reference cells with reference cell resistors. The memory cell array is configured such that for testing a respective cell resistor in each case two of the reference cell resistors nearest the respective cell resistor and the reference cell are simultaneously connected to a common word line voltage. A first feedback amplifier together with the two reference cell resistors form a summing amplifier. A second feedback amplifier together with the respective cell resistor form an amplifier having an equivalent gain as the summing amplifier. A comparator is connected to the summing amplifier and the amplifier. The comparator has an output supplying an evaluation signal dependent on the respective cell resistor.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: December 3, 2002
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Werner Weber
  • Patent number: 6487109
    Abstract: A magnetoresistive memory includes magnetoresistive memory cells disposed in a plurality of rows and/or columns. A bit line is connected to first poles of the memory cells of a column. A word line is connected to second poles of the memory cells of a row. A read voltage source is separately connectable to first ends of the word lines. A voltage evaluator has at least one input that is separately connectable to first ends of the bit lines via an evaluation line. A first terminating resistor branches from the evaluation line. An impedance converter has an input connected to the evaluation line and has an output separately connectable to second ends of the bit lines and word lines. The invention also relates to a method of reading magnetoresistive memories.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: November 26, 2002
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Werner Weber, Hugo Van Den Berg
  • Patent number: 6452850
    Abstract: A description is given of a sense amplifier subcircuit (10), for example an N latch section or a P latch section, for a DRAM memory for amplifying voltage signals read from a bit line (50), having at least two evaluation transistors (20; 30), the gate (21) of one evaluation transistor (20) being connected or connectable to at least one bit line (50) and the gate (31) of another evaluation transistor (30) being connected or connectable to at least one reference bit line (51) and the drains (23, 33) of the evaluation transistors (20; 30) being connected or connectable to the bit lines (51, 50) and the sources (22, 32) of the evaluation transistors (20; 30) being connected or connectable to a (NCS/PCS) lead (11).
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: September 17, 2002
    Assignee: Infineon Technologies AG
    Inventors: Alexander Frey, Werner Weber
  • Publication number: 20020126525
    Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.
    Type: Application
    Filed: April 1, 2002
    Publication date: September 12, 2002
    Inventors: Werner Weber, Roland Thewes
  • Patent number: 6445609
    Abstract: A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: September 3, 2002
    Assignee: Infineon Technologies AG
    Inventors: Alexander Frey, Werner Weber, Till Schlösser