Abstract: A description is given of a sense amplifier subcircuit (10), for example an N latch section or a P latch section, for a DRAM memory for amplifying voltage signals read from a bit line (50), having at least two evaluation transistors (20; 30), the gate (21) of one evaluation transistor (20) being connected or connectable to at least one bit line (50) and the gate (31) of another evaluation transistor (30) being connected or connectable to at least one reference bit line (51) and the drains (23, 33) of the evaluation transistors (20; 30) being connected or connectable to the bit lines (51, 50) and the sources (22, 32) of the evaluation transistors (20; 30) being connected or connectable to a (NCS/PCS) lead (11).

Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.

Abstract: A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another.

Abstract: A magneto resistive memory contains first switches, a word line voltage source generating a word line voltage connected to the first switches, a line node, second switches, and cells formed of cell resistors each having a first terminal connected to the word line voltage through one of the first switches and a second terminal connected to the line node through one of the second switches. A reference resistor is connected to the line node and a reference voltage source is connected to the reference resistor. The reference resistor with the reference voltage source brings about a reduction in a respective cell current, flowing from the line node, by an average current. A device is connected to the line node and evaluates the cell resistors. The device has an amplifier for converting a difference between the respective cell current and the average current into a voltage functioning as an evaluation signal.

Abstract: A magnetoresistive memory is described and contains a common word line voltage source, bit lines, word lines crossing the bit lines, and a memory cell array having memory cells with cell resistors. The memory cell array further has reference cells with reference cell resistors. The memory cell array is configured such that for testing a respective cell resistor in each case two of the reference cell resistors nearest the respective cell resistor and the reference cell are simultaneously connected to a common word line voltage. A first feedback amplifier together with the two reference cell resistors form a summing amplifier. A second feedback amplifier together with the respective cell resistor form an amplifier having an equivalent gain as the summing amplifier. A comparator is connected to the summing amplifier and the amplifier. The comparator has an output supplying an evaluation signal dependent on the respective cell resistor.

Abstract: A magnetoresistive memory includes magnetoresistive memory cells disposed in a plurality of rows and/or columns. A bit line is connected to first poles of the memory cells of a column. A word line is connected to second poles of the memory cells of a row. A read voltage source is separately connectable to first ends of the word lines. A voltage evaluator has at least one input that is separately connectable to first ends of the bit lines via an evaluation line. A first terminating resistor branches from the evaluation line. An impedance converter has an input connected to the evaluation line and has an output separately connectable to second ends of the bit lines and word lines. The invention also relates to a method of reading magnetoresistive memories.

Abstract: The magnetoresistive memory provides for an improvement in interference immunity even though only a small chip area is used. Word lines are situated vertically between two complementary bit lines, a magnetoresistive memory system of a regular location is situated between a bit line and a word line, and an appertaining magnetoresistive layer system of a complementary memory location is situated between the complementary bit line and the word line in the vertical direction.

Abstract: A description is given of a sense amplifier subcircuit (10), for example an N latch section or a P latch section, for a DRAM memory for amplifying voltage signals read from a bit line (50), having at least two evaluation transistors (20; 30), the gate (21) of one evaluation transistor (20) being connected or connectable to at least one bit line (50) and the gate (31) of another evaluation transistor (30) being connected or connectable to at least one reference bit line (51) and the drains (23, 33) of the evaluation transistors (20; 30) being connected or connectable to the bit lines (51, 50) and the sources (22, 32) of the evaluation transistors (20; 30) being connected or connectable to a (NCS/PCS) lead (11). According to the invention, at least one of the evaluation transistors (20; 30) is designed in such a way that its threshold voltage changes dynamically during the evaluation operation by virtue of the change in the gate voltage being coupled to a change in the body voltage.

Abstract: The clamping device is used to adjust at least one register element in a printing machine. The device has an upper clamping rail, to which the register element is fixed. The upper clamping rail can be moved in a guide and fixed in position in order to adjust the register element.

Abstract: The magnetoresistive memory provides for an improvement in interference immunity even though only a small chip area is used. Word lines are situated vertically between two complementary bit lines, a magnetoresistive memory system of a regular location is situated between a bit line and a word line, and an appertaining magnetoresistive layer system of a complementary memory location is situated between the complementary bit line and the word line in the vertical direction.

Abstract: A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.

Abstract: A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another.

Abstract: As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.

Abstract: The magnetoresistive memory has a reduced current density in the bit lines and/or word lines. This avoids electromigration problems. The current density is reduced such that a compact field concentration is attained, for example, by the use of ferrite in the area around the magnetic memory cells.

Abstract: The circuit arrangement has two electrical quantities in the form of a first quadrature-axis current component (I.sub.1) and of a second quadrature-axis current component (I.sub.2) that are compared to one another. The circuit arrangement has a first inverter unit (n.sub.1, p.sub.1) and a second inverter unit (n.sub.2, p.sub.2). Respectively one output (50, 52) of the two inverter units ((n.sub.1, p.sub.1, (n.sub.2, p.sub.2)) are coupled to an input of the respectively other inverter unit (52, 53). A reset unit (5) that initiates the comparison of the currents when activated is located between the two outputs of the two inverter units (n.sub.1, p.sub.2). When the reset unit (5) is deactivated, the output datum obtained in the evaluation remains stable.

Abstract: An associative memory contains cells that are formed of a series circuit of an ordinary PMOS transistor with a PMOS transistor with a floating gate. The ordinary PMOS transistor receives of an input vector and the gate of the second PMOS transistor is connected to a learning input. For the associative access, a second vector can be applied to the drain terminal of the second PMOS transistor and, upon readout, the current flow through the respective series circuit is evaluated column-by-column by current evaluator circuits.

Abstract: A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.

Abstract: In an electrically programmable read-only memory and method for the programming and reading of the memory, a self-convergent programming of a flash EEPROM is provided in which it is possible to rapidly and reliably set an inception voltage of a memory cell.

Abstract: The threshold value logic has a non-inverting circuit path (S) that and an inverting circuit path (S') are connected to at least one comparative weighting subcircuit (BC, BS). The non-inverting circuit path and the inverting circuit path preferably are of identical construction and each contain at least one neuron transistor (NT1, NT1'). The corresponding neuron transistor gates in the non-inverting circuit path and in the inverting circuit path are driven inversely with respect to one another.

Abstract: A digital/analog converter has a neuron MOS transistor, a maintenance circuit which keeps the drain potential of the neuron MOS transistor constant, and a current source. A linear dynamic range in terms of large signal is possible, so that converters having a larger input word size than, for example, only two bits can be realized in a simple way with low dissipated power. Such converters are of significance particularly for ULSI circuits.