Patents by Inventor Wesley H. Smith

Wesley H. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9430384
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: March 31, 2013
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Carlos V Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A Goldsmith, Barry E Huntley, Anton Ivanov, Simon P Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott Dion Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H Smith, William Colin Wood
  • Publication number: 20160202976
    Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
    Type: Application
    Filed: March 18, 2016
    Publication date: July 14, 2016
    Applicant: Intel Corporation
    Inventors: Rebekah Leslie-Hurd, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Barry E. Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis X. Mckeen, Michael A. Goldsmith, Ilya Alexandrovich, Alex Berenzon, Wesley H. Smith, Gilbert Neiger
  • Patent number: 9323686
    Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Francis X. Mckeen, Michael A. Goldsmith, Barry E. Huntley, Simon P. Johnson, Rebekah Leslie, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Ittai Anati, Ilya Alexandrovich, Alex Berenzon, Gilbert Neiger
  • Publication number: 20160042184
    Abstract: Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having an associated enclave page cache address. The execution unit is to execute the instruction without causing a virtual machine exit, wherein execution of the instruction includes logging the instruction and the associated enclave page cache address.
    Type: Application
    Filed: October 21, 2015
    Publication date: February 11, 2016
    Applicant: Intel Corporation
    Inventors: Francis X. Mckeen, Michael A. Goldsmith, Barrey E. Huntley, Simon P. Johnson, Rebekah M. Leslie-Hurd, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Gilbert Neiger
  • Patent number: 9189411
    Abstract: Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having an associated enclave page cache address. The execution unit is to execute the instruction without causing a virtual machine exit, wherein execution of the instruction includes logging the instruction and the associated enclave page cache address.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Francis X. Mckeen, Michael A. Goldsmith, Barrey E. Huntley, Simon P. Johnson, Rebekah Leslie, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith
  • Publication number: 20150089173
    Abstract: Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section are convertible in response to a section conversion instruction.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Inventors: Siddhartha Chhabra, Uday R. Savagaonkar, Michael A. Goldsmith, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Ittai Anati, Ilya Alexandrovich
  • Publication number: 20140297962
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Application
    Filed: March 31, 2013
    Publication date: October 2, 2014
    Inventors: CARLOS V ROZAS, ILYA ALEXANDROVICH, ITTAI ANATI, ALEX BERENZON, MICHAEL A GOLDSMITH, BARRY E HUNTLEY, ANTON IVANOV, SIMON P JOHNSON, REBEKAH M. LESLIE-HURD, FRANCIS X. MCKEEN, GILBERT NEIGER, RINAT RAPPOPORT, SCOTT DION RODGERS, UDAY R. SAVAGAONKAR, VINCENT R. SCARLATA, VEDVYAS SHANBHOGUE, WESLEY H SMITH, WILLIAM COLIN WOOD
  • Publication number: 20140189242
    Abstract: Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having an associated enclave page cache address. The execution unit is to execute the instruction without causing a virtual machine exit, wherein execution of the instruction includes logging the instruction and the associated enclave page cache address.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Francis X. Mckeen, Michael A. Goldsmith, Barrey E. Huntley, Simon P. Johnson, Rebekah Leslie, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith
  • Publication number: 20140189325
    Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Francis X. Mckeen, Michael A. Goldsmith, Barry E. Huntley, Simon P. Johnson, Rebekah Leslie, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Ittai Anati, Ilya Alexandrovich, Alex Berenzon
  • Publication number: 20140189326
    Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Rebekah Leslie, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Barry E. Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis X. Mckeen, Michael A. Goldsmith, Ilya Alexandrovich, Alex Berenzon, Wesley H. Smith
  • Patent number: 7486724
    Abstract: Methods and apparatus to perform and/or analyze communication channels are described. In one embodiment, a test signal may be generated and transferred using a first signal route to a line-under-test in response to line qualification mode. The first signal route may include a compensation device to modify the test signal. In some embodiments, a reflected signal from the line-under-test may be received in response to the test signal. A second signal route may be utilized to route the reflected signal in response to line qualification mode.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 3, 2009
    Assignee: Intel Corporation
    Inventors: Xiao M. Gao, Wesley H. Smith
  • Patent number: 7406157
    Abstract: Embodiments of the invention provide methods for determining the characteristics of a local loop using the multi-carrier tones of a DSL activation process. For one embodiment, one or more sets of downstream multi-carrier tones of a digital subscriber line activation process are received at an extended voice-band modem and are capable of transmitting upstream multi-carrier tones of the digital subscriber line activation process over a local loop. The downstream carrier tones and the upstream carrier tones are folded into a first multi-tone signal and a second multi-tone signal, respectively, each having a plurality of component signals within the spectrum band of the extended voice-based modem. The total signal power of the first multi-tone signal is divided by the power of one of the plurality of component signals of the second multi-tone signal to determine a ratio value. The ratio value is used to determine a characteristic of the local loop.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventors: Sigang Qiu, Prashant Pratap Tawade, Vedavalli G. Krishnan, Wesley H. Smith, Mandayam Krishnan
  • Publication number: 20070280208
    Abstract: Embodiments of apparatuses, articles, methods, and systems for voice communication components within a partition of a computing platform are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 6, 2007
    Inventors: Wesley H. Smith, Bo Zhang, Don Carmon, Mark Shanahan, Jeffrey A. Green
  • Patent number: 7133497
    Abstract: Lower bandwidth technology is used to determine whether a communication channel can support higher bandwidth technology. A signal generator generates a series of test signals that are associated with the higher bandwidth technology. The test signals are sampled to produce aliases that can be analyzed with lower bandwidth technology. Modem parameters are accessed from a modem's memory. The modem parameters are compared with a database containing information about whether a set of modem parameters indicates that a telephone local can support broadband devices.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Karl I. Nordling, Vedavalli G. Krishnan, Mandayam G. Krishnan, Fred Schuckert, Wesley H. Smith, Don Carmon
  • Patent number: 7103147
    Abstract: Embodiments of the invention provide methods and apparatuses to determine the characteristics of a local loop using the multi-tone line-probing signals of a standard voice-based modem. For one embodiment, the multi-tone, line-probing signals of a voice-band modem are transmitted over a local loop and received at a standard voice band modem. Discrete Fourier transform values are determined for each of two or more frequencies of the plurality of frequencies of the multi-tone signals. A set of discrete Fourier transform values corresponding to a set of high frequencies is summed to obtain a first value and a set of discrete Fourier transform values corresponding to a set of low frequencies is summed to obtain a second value. A power ratio is determined by dividing the first value by the second value. The power ratio is then used to determine a characteristic of the local loop.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Sigang Qiu, Prashant Pratap Tawade, Vedavalli G. Krishna, Wesley H. Smith, Mandayam G. Krishnan, Bo G. Zhang
  • Patent number: 7072462
    Abstract: A system for determining whether a telephone loop is capable of carrying a Digital Subscriber Line (DSL) signal. A Constant Amplitude Zero Auto Correlation (CAZAC) sequence signal is generated and transmitted through the loop plant to a central office and the received echo signal is processed using second-order statistics. The second-order statistics calculation permits determination of the echo signal amplitude and time between the echo signal and sequence signal. The echo signal amplitude and time may be used to obtain telephone loop characteristics such as loop length.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Wesley H. Smith, Veda Krishnan, Xiao M. Gao, Kanna Krishnan
  • Patent number: 7020246
    Abstract: An apparatus and technique for determining whether a telephone loop is capable of carrying a Digital Subscriber Line (DSL) signal. Time domain reflected (TDR) signals that are echoes of transmit impulse signals are processed using time domain echo averaging and echo enhancement using second-order statistics. Each technique allows clearer visualization of the TDR echo signal by reducing the noise and distortion present in the TDR signals. These statistical signal processing techniques allow determination of telephone loop characteristics such as loop length once the TDR echo signal amplitude and time index are calculated.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Xiao M. Gao, Wesley H. Smith, Veda Krishnan, Kanna Krishnan
  • Publication number: 20040267678
    Abstract: An apparatus and technique for Digital Subscriber Line (DSL) telephone loop qualification that includes a fuzzy logic impedance mismatch network. The impedance mismatch network is used to increase the received echo of a transmit pulse signal to determine the telephone loop characteristics.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Xiao M. Gao, Wesley H. Smith, Veda Krishnan, Kanna Krishnan
  • Publication number: 20040264685
    Abstract: A system for determining whether a telephone loop is capable of carrying a Digital Subscriber Line (DSL) signal. A Constant Amplitude Zero Auto Correlation (CAZAC) sequence signal is generated and transmitted through the loop plant to a central office and the received echo signal is processed using second-order statistics. The second-order statistics calculation permits determination of the echo signal amplitude and time between the echo signal and sequence signal. The echo signal amplitude and time may be used to obtain telephone loop characteristics such as loop length.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Wesley H. Smith, Veda Krishnan, Xiao M. Gao, Kanna Krishnan
  • Publication number: 20040264684
    Abstract: An apparatus and technique for determining whether a telephone loop is capable of carrying a Digital Subscriber Line (DSL) signal. Time domain reflected (TDR) signals that are echoes of transmit impulse signals are processed using time domain echo averaging and echo enhancement using second-order statistics. Each technique allows clearer visualization of the TDR echo signal by reducing the noise and distortion present in the TDR signals. These statistical signal processing techniques allow determination of telephone loop characteristics such as loop length once the TDR echo signal amplitude and time index are calculated.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Xiao M. Gao, Wesley H. Smith, Veda Krishnan, Kanna Krishnan