Patents by Inventor Wesley Shao
Wesley Shao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954058Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: GrantFiled: May 18, 2022Date of Patent: April 9, 2024Assignee: Futurewei Technologies, Inc.Inventor: Wesley Shao
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Publication number: 20220276976Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: ApplicationFiled: May 18, 2022Publication date: September 1, 2022Applicant: Futurewei Technologies, Inc.Inventor: Wesley Shao
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Patent number: 11429550Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: GrantFiled: January 20, 2021Date of Patent: August 30, 2022Assignee: Futurewei Technologies, Inc.Inventor: Wesley Shao
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Publication number: 20210216485Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: ApplicationFiled: January 20, 2021Publication date: July 15, 2021Applicant: Futurewei Technologies, Inc.Inventor: Wesley Shao
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Patent number: 10922259Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: GrantFiled: August 13, 2019Date of Patent: February 16, 2021Assignee: Futurewei Technologies, Inc.Inventor: Wesley Shao
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Publication number: 20200353832Abstract: Deep neural network (DNN) based driving assistance system is disclosed. For one example, a vehicle data processing system includes one or more sensors and a driving assistance system. The one or more sensors obtain data describing an environment around a vehicle. The driving assistance system is coupled to the one or more sensors and configured to detect continuously a designated object in the environment around the vehicle based on the captured data from the one or more sensors using a deep neural network (DNN). The driving assistance system is also configured to output commands from the DNN used to autonomously steer the vehicle to the designated object in the environment to enable coupling of the vehicle with the designated object, e.g., a charging pad for wireless charging.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventors: Xinhua Xiao, Wesley Shao
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Patent number: 10635621Abstract: An apparatus includes a chassis housing a control server compartment, a compute server compartment, and an input and output (IO) subsystem compartment. The apparatus further includes an IO subsystem inserted into the IO subsystem compartment, a compute server inserted into the compute server compartment, and a control server inserted into the control server compartment coupled to the compute server via an Ethernet connection. The IO subsystem includes one or more IO modules, where at least some of the IO modules can be coupled to sensors. The compute server receives the sensor data from the IO subsystem via some PCIe links and generates planning and control data based on the sensor data for controlling the autonomous vehicle. The control server controls and operates the autonomous vehicle by sending control commands to hardware of the autonomous vehicle based on the planning and control data received from the compute server.Type: GrantFiled: November 16, 2016Date of Patent: April 28, 2020Assignee: BAIDU USA LLCInventors: Wesley Shao, Ji Li, Wendy Lu, Andrew Yao, Junwei Bao, Davy Huang
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Publication number: 20200110722Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: ApplicationFiled: August 13, 2019Publication date: April 9, 2020Inventor: Wesley Shao
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Patent number: 10579310Abstract: A method for operating a device adapted to store information with high reliability includes determining a storage address for a data payload portion of a write request in accordance with a configuration of a communications interface coupled to the device, where the data payload is to be stored in mirroring groups of cache storage partitions of a plurality of cache storage modules. The method also includes generating a payload read request in accordance with the storage address, and prompting the communications interface to initiate the storing of the data payload, in parallel, in the mirroring groups in accordance with the payload read request.Type: GrantFiled: December 27, 2017Date of Patent: March 3, 2020Assignee: Futurewei Technologies, Inc.Inventors: Mark Allan Kampe, Cameron Bahar, Jinshui Liu, Wesley Shao, Huawei Liu
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Patent number: 10417160Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: GrantFiled: June 15, 2018Date of Patent: September 17, 2019Assignee: FutureWei Technologies, Inc.Inventor: Wesley Shao
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Patent number: 10216676Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: GrantFiled: June 15, 2018Date of Patent: February 26, 2019Assignee: FutureWei Technologies, Inc.Inventor: Wesley Shao
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Patent number: 10210124Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: GrantFiled: August 10, 2015Date of Patent: February 19, 2019Assignee: FutureWei Technologies, Inc.Inventor: Wesley Shao
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Patent number: 10162792Abstract: In one embodiment, a dedicated time processing device inserted into a peripheral bus coupling or embedded with at least some of the rest of system components (e.g., processor, memory) of a data processing system to synchronize a system clock of the data processing system. The peripheral bus can be a Peripheral Component Interface (PCI) bus, a PCI Express (PCIe) link, a PCI extended (PCI-X) bus, or the like. The time processing device receives high precision time from a high precision time source, such as global positioning system (GPS) time source. The time processing device decodes and processes the received time and stores the time in an internal time register. The time processing device further includes an interface to allow an external component (e.g., a processor) to retrieve with low latency the time stored in the time register for the purpose of synchronizing the system clock.Type: GrantFiled: October 13, 2016Date of Patent: December 25, 2018Assignee: BAIDU USA LLCInventors: Wesley Shao, Vivek Surabhi
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Patent number: 10133698Abstract: An IO subsystem chassis includes IO modules and IO slots to receive the IO modules inserted from a frontend of a housing, a baseboard disposed within the housing, the baseboard including first connectors corresponding to the IO slots to receive and connect the IO modules. Each of the IO modules can be coupled a server via the backend panel using a cable. Each IO module includes an IO card having a peripheral device mounted thereon and a card holder having a first receiving socket to receive and hold the IO card plugged in vertically and downwardly. The card holder further includes a second connector to engage with or disengage from a corresponding one of the first connectors of the baseboard horizontally, when the IO module is inserted into or removed from a corresponding IO slot from the frontend, without having to removing the housing.Type: GrantFiled: February 9, 2016Date of Patent: November 20, 2018Assignee: BAIDU USA LLCInventors: Wesley Shao, Ji Li, Junwei Bao, Weiyu Wendy Lu
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Publication number: 20180300276Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: ApplicationFiled: June 15, 2018Publication date: October 18, 2018Inventor: Wesley Shao
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Publication number: 20180300277Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.Type: ApplicationFiled: June 15, 2018Publication date: October 18, 2018Inventor: Wesley Shao
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Publication number: 20180137076Abstract: An apparatus includes a chassis housing a control server compartment, a compute server compartment, and an input and output (IO) subsystem compartment. The apparatus further includes an IO subsystem inserted into the IO subsystem compartment, a compute server inserted into the compute server compartment, and a control server inserted into the control server compartment coupled to the compute server via an Ethernet connection. The IO subsystem includes one or more IO modules, where at least some of the IO modules can be coupled to sensors. The compute server receives the sensor data from the IO subsystem via some PCIe links and generates planning and control data based on the sensor data for controlling the autonomous vehicle. The control server controls and operates the autonomous vehicle by sending control commands to hardware of the autonomous vehicle based on the planning and control data received from the compute server.Type: ApplicationFiled: November 16, 2016Publication date: May 17, 2018Inventors: WESLEY SHAO, JI LI, WENDY LU, ANDREW YAO, JUNWEI BAO, DAVY HUANG
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Publication number: 20180121138Abstract: A method for operating a device adapted to store information with high reliability includes determining a storage address for a data payload portion of a write request in accordance with a configuration of a communications interface coupled to the device, where the data payload is to be stored in mirroring groups of cache storage partitions of a plurality of cache storage modules. The method also includes generating a payload read request in accordance with the storage address, and prompting the communications interface to initiate the storing of the data payload, in parallel, in the mirroring groups in accordance with the payload read request.Type: ApplicationFiled: December 27, 2017Publication date: May 3, 2018Inventors: Mark Allan Kampe, Cameron Bahar, Jinshui Liu, Wesley Shao, Huawei Liu
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Publication number: 20180107626Abstract: In one embodiment, a dedicated time processing device inserted into a peripheral bus coupling or embedded with at least some of the rest of system components (e.g., processor, memory) of a data processing system to synchronize a system clock of the data processing system. The peripheral bus can be a Peripheral Component Interface (PCI) bus, a PCI Express (PCIe) link, a PCI extended (PCI-X) bus, or the like. The time processing device receives high precision time from a high precision time source, such as global positioning system (GPS) time source. The time processing device decodes and processes the received time and stores the time in an internal time register. The time processing device further includes an interface to allow an external component (e.g., a processor) to retrieve with low latency the time stored in the time register for the purpose of synchronizing the system clock.Type: ApplicationFiled: October 13, 2016Publication date: April 19, 2018Inventors: WESLEY SHAO, VIVEK SURABHI
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Patent number: 9875208Abstract: A method for accessing a device in a primary peripheral component interconnect express (PCIe) domain from a secondary PCIe domain includes determining which one or more virtual functions of the device in the primary PCIe domain are to be made available to the secondary PCIe domain. A virtual function driver is installed in the primary PCIe domain associated with the one or more virtual functions. Information corresponding to the one or more virtual functions is provided to the secondary PCIe domain. A virtual function driver associated with the one or more virtual functions is installed in the secondary PCIe domain from the information. The virtual function driver in the secondary PCIe domain has same properties as the virtual function driver in the primary PCIe domain. The device in the primary PCIe domain is accessed from the virtual function driver in the secondary PCIe domain.Type: GrantFiled: October 2, 2015Date of Patent: January 23, 2018Assignee: FUTUREWEI TECHNOLOGIES, INC.Inventors: Thomas Boyle, Chang Yu, Wesley Shao, Ligang Chen