Abstract: A method for operating a device adapted to store information with high reliability includes determining a storage address for a data payload portion of a write request in accordance with a configuration of a communications interface coupled to the device, where the data payload is to be stored in mirroring groups of cache storage partitions of a plurality of cache storage modules. The method also includes generating a payload read request in accordance with the storage address, and prompting the communications interface to initiate the storing of the data payload, in parallel, in the mirroring groups in accordance with the payload read request.

Abstract: An IO subsystem chassis includes IO modules and IO slots to receive the IO modules inserted from a frontend of a housing, a baseboard disposed within the housing, the baseboard including first connectors corresponding to the IO slots to receive and connect the IO modules. Each of the IO modules can be coupled a server via the backend panel using a cable. Each IO module includes an IO card having a peripheral device mounted thereon and a card holder having a first receiving socket to receive and hold the IO card plugged in vertically and downwardly. The card holder further includes a second connector to engage with or disengage from a corresponding one of the first connectors of the baseboard horizontally, when the IO module is inserted into or removed from a corresponding IO slot from the frontend, without having to removing the housing.

Abstract: A method for extending a Peripheral Component Interconnect Express (PCIe) domain. A configuration space address can be allocated to a PCIe device in an extended domain from a memory address of a root complex endpoint device, a correspondence between the configuration space address and a bus number/device number/function number (BDF) can be established, and a bus number can be allocated from a second bus set of the extended domain to a PCIe device discovered in the extended domain, where the bus number is used for determining the BDF of the PCIe device discovered in the extended domain, so as to access, according to the correspondence between the configuration space address and the BDF and by using the BDF of the PCIe device discovered in the extended domain, a configuration space register of the PCIe device discovered in the extended domain.

Abstract: A method for operating a device adapted to store information with high reliability includes determining a storage address for a data payload portion of a write request in accordance with a configuration of a communications interface coupled to the device, where the data payload is to be stored in mirroring groups of cache storage partitions of a plurality of cache storage modules. The method also includes generating a payload read request in accordance with the storage address, and prompting the communications interface to initiate the storing of the data payload, in parallel, in the mirroring groups in accordance with the payload read request.

Abstract: A method for accessing a device in a primary peripheral component interconnect express (PCIe) domain from a secondary PCIe domain includes determining which one or more virtual functions of the device in the primary PCIe domain are to be made available to the secondary PCIe domain. A virtual function driver is installed in the primary PCIe domain associated with the one or more virtual functions. Information corresponding to the one or more virtual functions is provided to the secondary PCIe domain. A virtual function driver associated with the one or more virtual functions is installed in the secondary PCIe domain from the information. The virtual function driver in the secondary PCIe domain has same properties as the virtual function driver in the primary PCIe domain. The device in the primary PCIe domain is accessed from the virtual function driver in the secondary PCIe domain.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: Per-Function Downstream Port Containment (pF-DPC) is an extension to Downstream Port Containment (DPC) in the Peripheral Component Interconnect express (PCIe) standard. Pf-DPC confines non-fatal errors to specific functions of an end-point device without disabling the link between a PCIe port and the end-point device. PCIe ports configured for pF-DPC may filter (e.g., drop) packets carrying routing identifiers (RIDs) and/or addresses assigned to a function affected by a non-fatal error, while continuing to forward packets carrying RIDs/addresses associated with remaining operable functions over the corresponding link.

Abstract: A method for extending a Peripheral Component Interconnect Express (PCIe) domain. A configuration space address can be allocated to a PCIe device in an extended domain from a memory address of a root complex endpoint device, a correspondence between the configuration space address and a bus number/device number/function number (BDF) can be established, and a bus number can be allocated from a second bus set of the extended domain to a PCIe device discovered in the extended domain, where the bus number is used for determining the BDF of the PCIe device discovered in the extended domain, so as to access, according to the correspondence between the configuration space address and the BDF and by using the BDF of the PCIe device discovered in the extended domain, a configuration space register of the PCIe device discovered in the extended domain.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: Per-Function Downstream Port Containment (pF-DPC) is an extension to Downstream Port Containment (DPC) in the Peripheral Component Interconnect express (PCIe) standard. Pf-DPC confines non-fatal errors to specific functions of an end-point device without disabling the link between a PCIe port and the end-point device. PCIe ports configured for pF-DPC may filter (e.g., drop) packets carrying routing identifiers (RIDs) and/or addresses assigned to a function affected by a non-fatal error, while continuing to forward packets carrying RIDs/addresses associated with remaining operable functions over the corresponding link.

Abstract: A method that includes creating a DMA group, adding a first I/O device to the DMA group, and adding a second I/O device to the DMA group. The method further includes instructing an I/O MMU to create a shared virtual DMA address, mapping a memory location to the shared virtual DMA address in the DMA group translation table, and providing the shared virtual DMA address to the device drivers. The method further includes determining that the first I/O device has received DMA group data, instructing a first DMA controller to transfer the DMA group data from the first I/O device to the shared virtual DMA address, determining that the shared virtual DMA address has received the DMA group data, and instructing a second DMA controller to transfer the DMA group data from the memory location corresponding to the shared virtual DMA address to the second I/O device.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A method that includes creating a DMA group, adding a first I/O device to the DMA group, and adding a second I/O device to the DMA group. The method further includes instructing an I/O MMU to create a shared virtual DMA address, mapping a memory location to the shared virtual DMA address in the DMA group translation table, and providing the shared virtual DMA address to the device drivers. The method further includes determining that the first I/O device has received DMA group data, instructing a first DMA controller to transfer the DMA group data from the first I/O device to the shared virtual DMA address, determining that the shared virtual DMA address has received the DMA group data, and instructing a second DMA controller to transfer the DMA group data from the memory location corresponding to the shared virtual DMA address to the second I/O device.

Abstract: A method comprising: sending an I/O message to an I/O device on an I/O bus, wherein the I/O device comprises an I/O device state, wherein the first I/O message is a I/O traffic type; receiving a LSR suspend request comprising a suspend instruction to suspend the I/O traffic type, an expected impact, and an I/O device identifier associated with the I/O device; setting the I/O device state to suspended in response to the receiving the LSR suspend request, wherein no I/O messages of the I/O traffic type are sent to the I/O device while the I/O device state is suspended; receiving a LSR resume request comprising a resume instruction to resume the I/O traffic type, the expected impact, and the I/O device identifier; setting the I/O device state to online in response to the receiving the LSR resume request; and sending a second I/O message to the I/O device.

Abstract: A device list is created for an operating system and/or a virtualized operating system. A bus node is created for each bus. Interface nodes are created as child nodes of the respective bus and a status indicator indicates whether a device connected to the interface is accessible. A device node is created for the device connected to the interface. Virtualized interface nodes are created as child nodes of the device node for each virtual device included in the device and a status indicator indicates whether the respective virtual device is accessible. Then, devices and/or virtual devices may be added and/or removed utilizing the list. After a device and/or virtualized device has been removed for one operating system and/or virtualized operating system, it may then be added to another. In this way, devices and/or virtualized devices can be virtually hot plugged without physically connecting and/or disconnecting devices.

Abstract: A device list is created for an operating system and/or a virtualized operating system. A bus node is created for each bus. Interface nodes are created as child nodes of the respective bus and a status indicator indicates whether a device connected to the interface is accessible. A device node is created for the device connected to the interface. Virtualized interface nodes are created as child nodes of the device node for each virtual device included in the device and a status indicator indicates whether the respective virtual device is accessible. Then, devices and/or virtual devices may be added and/or removed utilizing the list. After a device and/or virtualized device has been removed for one operating system and/or virtualized operating system, it may then be added to another. In this way, devices and/or virtualized devices can be virtually hot plugged without physically connecting and/or disconnecting devices.

Abstract: According to one embodiment of the invention, a technique is provided for facilitating the relocation of data from a source page to a destination page in a computing system in which I/O devices may conduct DVMA transactions via an IOMMU. Before the relocation, it is determined whether any devices potentially are accessing the source page. If it is determined that a device potentially is accessing the source page, then the IOMMU's device driver (“bus nexus”) “suspends” the bus. The bus nexus allows any pending memory transactions to finish. While the bus is suspended, the kernel moves the contents of the source page to the destination page. After the kernel has moved the contents, the IOMMU's TLB is updated so that the virtual address that was mapped to the source page's physical address is mapped to the destination page's physical address. The bus nexus “unsuspends” the bus.

Abstract: According to one embodiment of the invention, a technique is provided for facilitating the relocation of data from a source page to a destination page in a computing system in which I/O devices may conduct DVMA transactions via an IOMMU. Before the relocation, it is determined whether any devices potentially are accessing the source page. If it is determined that a device potentially is accessing the source page, then the IOMMU's device driver (“bus nexus”) “suspends” the bus. The bus nexus allows any pending memory transactions to finish. While the bus is suspended, the kernel moves the contents of the source page to the destination page. After the kernel has moved the contents, the IOMMU's TLB is updated so that the virtual address that was mapped to the source page's physical address is mapped to the destination page's physical address. The bus nexus “unsuspends” the bus.