Abstract: Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions.

Abstract: A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.

Abstract: The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.

Abstract: A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.

Abstract: In a communication network operating according to a communication protocol that defines a link establishment procedure having i) a negotiating procedure and ii) a training procedure, a first communication device performs the link establishment procedure with a second communication device. During the negotiating procedure, the first communication device negotiates one or more new parameter values for the link establishment procedure that are different than one or more mandated parameter values specified by the communication protocol. During the link establishment procedure, the first communication device uses the one or more new parameter values instead of using the one or more mandated parameter values specified by the communication protocol.

Abstract: In an optical communication system, a high-speed data interface to an optical module can be configured from the module's host-side interface and line-side interface. These module interfaces can be configured with an integrated digital signal processor (DSP) having a DSP microcontroller unit (MCU) as a high-speed in-band DSP management interface. The DSP MCU can communicate to either a host MCU in a host switch/router via the host-side interface or to an external device through the optics hardware via the line-side interface. The present invention provides for systems, devices, and methods using this interface for numerous module DSP-related applications, such as firmware upgrades, management data, diagnostic/telemetry streaming, encryption key programming, and the like.

Abstract: The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.

Abstract: The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.

Abstract: A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.

Abstract: The present invention is direct to data communication. In a specific embodiment, multiple independent data streams, which are at a first data rate, are transcoded by separate communication pipelines into data blocks. The data blocks, associated with these separate and independent data streams, are multiplexed with alignment markers to generate an output data stream. The output data stream is transmitted at a second data rate, which is higher than the first data rate.

Abstract: The present invention is direct to data communication. In a specific embodiment, multiple independent data streams, which are at a first data rate, are transcoded by separate communication pipelines into data blocks. The data blocks, associated with these separate and independent data streams, are multiplexed with alignment markers to generate an output data stream. The output data stream is transmitted at a second data rate, which is higher than the first data rate.

Abstract: Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.

Abstract: Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described.

Abstract: An integrated circuit comprises a circuit module, a first function circuit, and a second function circuit. The first function circuit is configured to be operational in response to a first type logic signal at a first pin and the second function circuit is configured to be operational in response to a second type logic signal at the first pin. The type of logic signal at the first pin is determined by the circuit module. Based on the determined type of logic signal, the circuit module is configured to activate the appropriate function circuit and provide function related signaling for operation at a second pin. The circuit module allows the pins of the integrated circuit to be shared between the first and second function circuits, thus minimizing the number of pins required for multi-functional circuits on the integrated circuit.

Abstract: Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described.

Abstract: A process to manage data between one or more MDIO manageable devices situated on the same bus utilizing the MDIO protocol. The data management efficiency can be increased through the use of an MDIO protocol that includes a page-write mode. The MDIO protocol including the page-write mode can reduce the overhead for a write operation by omitting various portions of the MDIO communication frame format, including the preamble, start-of-frame, operational code, port address, device address, and turn-around fields that generally precede data to be written. The MDIO protocol including the page-write mode may include a next-data code to initiate the page-write mode.

Abstract: A process to manage data between one or more MDIO manageable devices situated on the same bus utilizing the MDIO protocol. The data management efficiency can be increased through the use of an MDIO protocol that includes a checksum mode. The MDIO protocol including the checksum mode can provide write confirmations while reducing the overhead for confirmed write operations by omitting read-back and compare sequences following write transactions.

Abstract: Methods, systems, and apparatuses are described for aligning lanes of low speed serial links coupled to a transceiver. The transceiver cooperatively performs lane alignment operations with a low speed device during initialization of the transceiver and the low speed device. The lane alignment operations are performed in-band using the low speed serial links, and therefore, do not require additional out-of-band-signaling wires between the transceiver and the low speed device to perform the lane alignment operations. The lane alignment operations may be performed by a handshaking process performed by the transceiver and the low speed device, where the transceiver and the low speed device provide training pattern(s) of data that are used to align the low speed serial links. The low speed serial links are continuously monitored after initialization is complete to detect various transient impairments and to re-initiate lane alignment operations in response to detecting such impairments.

Abstract: A process to manage data between one or more MDIO manageable devices situated on the same bus utilizing the MDIO protocol. The data management efficiency can be increased through the use of an MDIO protocol that includes a page-write mode. The MDIO protocol including the page-write mode can reduce the overhead for a write operation by omitting various portions of the MDIO communication frame format, including the preamble, start-of-frame, operational code, port address, device address, and turn-around fields that generally precede data to be written. The MDIO protocol including the page-write mode may include a next-data code to initiate the page-write mode.

Abstract: Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described.