Abstract: An integrated circuit comprises a circuit module, a first function circuit, and a second function circuit. The first function circuit is configured to he operational in response to a first type logic signal at a first pin and the second function circuit is configured to be operational in response to a second type logic signal at the first pin. The type of logic signal at the first pin is determined by the circuit module. Based on the determined type of logic signal, the circuit module is configured to activate the appropriate function circuit and provide function related signaling for operation at a second pin. The circuit module allows the pins of the integrated circuit to be shared between the first and second function circuits, thus minimizing the number of pins required for multi-functional circuits on the integrated circuit.

Abstract: A network communication system and method providing a communication protocol extension for direct memory access operations allowing the separation of the command and data paths. The identification of the communication path to a third-party device is provided to a direct-memory-access initiator allowing the passing of data directly to the third-party device.

Abstract: A network system gateway and method providing remote direct memory access controls to separate data path from control path. Control operations are passed between the gateway and a control processor node, and data is passed between the gateway and a memory node via remote direct memory access operations. The memory node may also receive instructions for the remote direct memory access operations through proxy remote direct memory access messages received from the control processor node.

Abstract: Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.

Abstract: The invention provides a networking system, network system gateway, and method for managing the transfer of data between networks interconnected through the gateway. The gateway manages the communication paths and commands used in transferring data, as well as the logins associated with each network. The gateway further provides the ability to buffer data in order to accommodate latencies within the networks. Additionally, the gateway provides the ability to pipeline data across the networks.

Abstract: Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.

Abstract: Broadly speaking, a device for addressing a shared resource is disclosed. The device includes at least one register in communication with the shared resource. The at least one register is configured to hold an address that is to be provided to the shared resource upon receipt of a clock signal. The device also includes a multiplexer for providing a next address to the at least one register. The multiplexer is disposed outside of a critical timing path for addressing the shared resource. The device for addressing the shared resource allows multiple users to be connected to the shared resource without adversely affecting both a speed of the shared resource and a number of users that can be achieved in an actual implementation of the shared resource.

Abstract: Broadly speaking, a bandwidth matching device is provided for transforming a number of incoming data streams each having a first bandwidth into an outgoing data stream having a second bandwidth. More specifically, the bandwidth matching device provides an assembler and a disassembler. The assembler incorporates a stepped arrangement of cells for transforming the number of incoming data streams having a given bandwidth into an outgoing data stream having a larger bandwidth, wherein each portion of the outgoing data stream represents a concatenation of a number of portions of each of the incoming data streams. As a complement to the assembler, the disassembler uses a stepped arrangement of cells to transform the concatenated output generated by the assembler back into the number of incoming data streams originally received by the assembler.

Abstract: An embodiment of the invention provides a method for creating a snapshot of a data store. A command to create a snapshot of an original data store, stored to a parent virtual logical unit (VLU), is received. A deferred propagation data structure (DPDS) is associated with the parent VLU. The DPDS is capable of containing data propagation records and separators, each data propagation record contains a previous version of one or more data blocks of the parent VLU, each separator contains a pointer to a particular child VLU storing a snapshot of the original data store and separating the data propagation records pertaining to the particular child VLU. A child VLU to store the copy of the original data store is created. A new separator containing a pointer to the child VLU is created in the DPDS. A search pointer pointing to the DPDS is implemented in the child VLU.

Abstract: In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations in memory and multiple distinct regions on one or more disks accessible to the DMA disk controller. The DMA disk controller further includes data manipulation logic to transfer data between the memory locations and the distinct regions on the disks according to the data transfer command.

Abstract: Broadly speaking, an apparatus for efficiently utilizing a shared packet buffer memory in a switch and a method for operating the same is provided. More specifically, the apparatus includes a memory having a number of buffers configured to be operated in a ratcheted manner. The ratcheted manner in which the memory is operated causes each incoming data stream to be distributed across the number of buffers. Each stored data stream can also be retrieved from the number of buffers for output from the memory in a similar ratcheted manner. The memory uses a rotating selector to control the ratcheted manner of operation. Also, the memory is capable of simultaneously servicing each of a number of inputs and a number of outputs to which the memory is connected.

Abstract: A metadata tree structure having a plurality of nodes (slabs), each node containing a MD table. Each of the MD tables has a plurality of entries. Each of the entries in the MD tables represents a contiguous range of block addresses and contains a pointer to a cache slot storing a date block corresponding to the block address, or an indicator to indicate that the corresponding data block is not stored in a NVRAM cache slot. Each MD table also contains a block address range indicator to indicate the contiguous range of block addresses, and at least one pointer to point to any parent or child nodes. In an alternative embodiment, the pointer of each MD entry may point to a disk address if the data is not in cache. For such an embodiment, portions of the MD store may be stored to disk.

Abstract: Embodiments of the present invention provide methods and systems for data movement in data storage systems. For one embodiment, a physical data storage parcel containing a first type of data requiring a first type of processing and a second type of data requiring a second type of processing is created. The first type of data is transferred to a first memory address space via a direct memory access operation and the second type of data is transferred to a second memory address space via the direct memory access operation. For one embodiment, the first type of data and the second type of data are copied to physically distinct data storage mediums. In an alternative embodiment, the first type of data and the second type of data are copied to distinct data storage structures of the same device. Thus, the bulk memory access operations are performed via hardware, thereby reducing performance impact.

Abstract: Embodiments of the present invention provide methods and apparatuses for accessing MD atomically. For one embodiment, the local cache and the remote cache are each provided with an MBE. To perform an atomic access operation, the local processing system allocates a burst descriptor buffer. The burst descriptor buffer is used to specify the addresses to be atomically accessed. For write operations, the burst descriptor buffer also specifies the update data. The addresses, and data, if any, are then transmitted to the remote cache as a series of packets constituting a single data access request. The MBE of the remote cache then performs the operations contained in the request. Upon completion of all of the operations the remote MBE transmits an acknowledgement. For read operations the remote MBE also transmits the requested data.

Abstract: A data storage system is disclosed in which a 3-party hand-off protocol is utilized to maintain a single coherent logical image. In particular, the functionality of the data storage system is separated into distinct processing modules. Each processing module is implemented in a distinct central processing unit (CPU). Alternatively, the first type processing module and the third type processing module can be implemented in a common CPU. Isolating the different functions of the data storage system into distinct CPUs facilitates failure recovery. A characteristic of the 3-party hand-off protocol is that, if an abnormal state occurs, a surviving module has sufficient information to proceed to recover from said abnormal state after detecting the abnormal state, without depending on a failing module, by retrying the data storage operation with another processing module or the failing module or cleaning up after the failed data storage operation, resulting in improved failure recovery.

Abstract: Various embodiments of systems and methods for implementing a streaming I/O protocol are disclosed. In some embodiments, a method may involve: receiving a packet initiating a streaming write operation, where the packet indicates that the size of the streaming write is larger than the size of the packet; initiating a write access having a size larger than the size of the packet to a storage device; receiving subsequent packets included in the streaming write operation; and writing data received in the subsequent packets to the storage device as part of the write access initiated in response to the earlier packet. In some embodiments, streaming read operations may also be supported.

Abstract: A method for creating a point-in-time copy of a data store. A command to create a point-in-time copy of an original data store is received. The processing of input/output operations to the original data store is suspended. A metadata structure of a copy data store is created. The metadata structure contains a null metadata slab tree, a backing store register, and a copy record, the copy record containing a pointer to a metadata structure of the original data store, the metadata structure of the original data store containing a pointer to the metadata structure of the copy data store. The processing of input/output operations to the original data store and to the copy data store is resumed.

Abstract: An embodiment of the invention provides a method for improving efficiency in a system containing repeated snapshots of an original data store. A READ/WRITE enabled parent virtual logical unit (VLU) to store an original data store is created. One or more READ-only enabled child VLUs, each storing a point-in-time copy of the original data store, are created at distinct times. A search pointer and a propagation pointer are implemented on the parent VLU and on each child VLU. The search pointer of each child VLU is set to point to the next subsequently created child VLU, with the search pointer of a most recently created child VLU set to point to the parent VLU. The propagation pointer of each child VLU is set to point to the immediately previously created child VLU, with the propagation pointer of the parent VLU set to point to the most recently created child VLU.

Abstract: A memory system is disclosed in which hardware assisted leases are utilized to control access to shared data resources among data users. The lease is a type of lock on content in the memory system that automatically expires after a preset period of time. The lease enables the lease owner exclusive use of the associated content in the memory system. Furthermore, the memory system has a memory access mechanism that is separate from the data users. The memory access mechanism includes hardware components to enforce lease-based access to the memory system. Since the lease expires rather than being permanently granted, no CPU or software thread is able to monopolize a lease forever. Moreover, since the lease-base access is hardware-assisted, faulty CPUs or software are prevented from unauthorized access to leased (or locked) content in which another CPU or software already holds a lease.

Abstract: A data storage system is disclosed in which a 3-party hand-off protocol is utilized to maintain a single coherent logical image. In particular, the functionality of the data storage system is separated into distinct processing modules. There are at least three types of processing modules. These three kinds of processing modules function cooperatively to perform data storage operations via the 3-party hand-off protocol. At least two types of processing modules are required to cooperate in a hand-off manner to fully execute each data storage operation.