Abstract: The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

Abstract: A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

Abstract: A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material.

Abstract: The present invention relates to a semiconductor device and a method of fabricating the same. In an embodiment of the present invention, an insulating layer in which contact holes are formed is formed over a semiconductor substrate in which lower metal lines are formed. A barrier metal layer, having a stack structure of a first tungsten (W) layer and a tungsten nitride (WN) layer, is formed within the contact holes. Contact plugs are formed within the contact holes.

Abstract: The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.

Abstract: In one aspect of the inventive method, a tunnel insulating film, a first conductive layer, and an isolation mask pattern are formed over a semiconductor substrate. The first conductive layer and the tunnel insulating film are patterned along the isolation mask pattern. A trench is formed in the semiconductor substrate. The trench is gap filled with a first insulating film. A polishing process is performed in order to expose the first conductive layer. A height of the first insulating film is lowered. The first conductive layer on the first insulating film is gap-filled with a second insulating film.

Abstract: A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.

Abstract: In a method of fabricating a flash memory device, after an isolation trench is formed, a bottom surface and sidewalls of the trench are gap-filled with a HARP film having a favorable step coverage. A wet etch process is performed such that the HARP film remains on the sidewalls of a tunnel dielectric layer, thereby forming a wing spacer. Accordingly, the tunnel dielectric layer can be protected and an interference phenomenon can be reduced because a control gate to be formed subsequently is located between floating gates.

Abstract: The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer.

Abstract: An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.

Abstract: The present invention discloses a method of manufacturing a flash memory device comprising the steps of forming a first insulating layer and a first conductive layer on a semiconductor substrate; etching the first conductive layer, the first insulating layer and the semiconductor substrate to form a trench; forming an isolation layer on a region on which the trench is formed; forming a second conductive layer to make the second conductive layer contact with the first conductive layer; and removing the second conductive layer formed on the isolation layer.

Abstract: Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly gates, forming a spacer at the side of the poly gate, forming a sacrifice nitride film on the entire surface, and then forming an interlayer insulation film on the entire surface, polishing the sacrifice nitride film formed on the interlayer insulation film and the poly gates so that the nitride film is exposed, removing top portions of the sacrifice nitride film while removing the nitride film, forming an insulation film spacer at the side exposed through removal of the nitride film, and filling a portion from which the sacrifice oxide film is removed with an insulation film, and forming the tungsten gates in portions from which the nitride films are moved.

Abstract: A method of forming a metal line in a semiconductor device, including the steps of forming a metal line in a semiconductor device in which dummy patterns are formed on a dummy region by using non-metal material when a metal line is formed through a damascene process to prevent a formation of an oxide layer on an aluminum layer caused by a slurry and cleaning solution used in the chemical mechanical polishing (CMP) process and carry out an uniform polishing process, whereby it is possible to prevent a digging phenomenon on a metal layer from being generated.

Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Abstract: A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.

Abstract: The present invention relates to a method of manufacturing a flash memory device. The method includes the steps of forming cell gate patterns and select transistor gate patterns on a semiconductor substrate; forming a low dielectric layer on the resultant structure; etching the low dielectric layer, leavinin gaps adjacent the cell gate patterns; and, forming a nitride layer spacer on one side wall of each of the select transistor gate patterns. The resulting flash memory device has an improved rate of change in the threshold voltage and reduces the contact resistance when a self-aligned contact method is subsequently performed.

Abstract: A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.

Abstract: A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

Abstract: A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.