Abstract: A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming an interlayer insulating layer and an etch-stop nitride layer over a semiconductor substrate, etching the etch-stop nitride layer and the interlayer insulating layer to form contact holes, forming contacts in the contact holes, forming an oxide layer on the entire surface including the contacts, etching the oxide layer using the etch-stop nitride layer as a target, thus forming trenches through which the contacts and the etch-stop nitride layer adjacent to the contacts are exposed, and forming bit lines in the trenches.

Abstract: A method of manufacturing semiconductor devices includes forming a trench in a predetermined region of a substrate. A first insulating layer and a second insulating layer are formed on a entire surface so that the trench is gap-filled. The first and second insulating layers are polished until a top surface of the substrate is exposed. A wet etch process of a low selectivity is performed, so that a portion of the first insulating layer remains on sides of the trench while stripping the second insulating layer. A third insulating layer is formed on the entire surface, so that the trench is gap-filled, thereby forming an isolation structure.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device. The method includes forming an etch-stop film on a semiconductor substrate in which a predetermined structure is formed, and then forming an interlayer insulating film. The method also includes etching a predetermined region of the interlayer insulating film, and then stopping the etch process at the etch-stop film, to form a damascene pattern. The method employs an etch-stop film made of a material having a low dielectric constant. Accordingly, an increase in the capacitance due to an etch-stop film formed of the existing material having a high dielectric constant can be prevented. It is therefore possible to prevent a reduction of RC delay and also to accelerate the operating speed of devices.

Abstract: Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly gates, forming a spacer at the side of the poly gate, forming a sacrifice nitride film on the entire surface, and then forming an interlayer insulation film on the entire surface, polishing the sacrifice nitride film formed on the interlayer insulation film and the poly gates so that the nitride film is exposed, removing top portions of the sacrifice nitride film while removing the nitride film, forming an insulation film spacer at the side exposed through removal of the nitride film, and filling a portion from which the sacrifice oxide film is removed with an insulation film, and forming the tungsten gates in portions from which the nitride films are moved.