Abstract: The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

Abstract: Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature.

Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization. Other embodiments include providing a substrate in a processing chamber and forming a copper seed layer on the substrate.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

Abstract: An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.

Abstract: A metal layer formed on a semiconductor wafer is planarized by applying sequentially a deplating step, a plating step, and a relaxation step in a removal cycle. A series of cycles are performed sequentially in one embodiment to comprise a pass. The removal cycle is repeated in sequence until the pass is completed. The respective deplating and plating rates are adjusted so that the ratios of deplating rates to plating rates progressively decrease from an initial pass to a final pass. Organic additives are added to the electrolytic plating solution to control the plating portion of the cycle in a topography dependant fashion.

Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

Abstract: A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.

Abstract: A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.