Patents by Inventor Wilbur Catabay

Wilbur Catabay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050064708
    Abstract: Embodiments of the invention include a method for forming copper interconnect structure. The method involves providing a substrate having a copper conductive layer formed thereon. An insulating layer having openings is formed on the conductive layer so that the openings expose portions of the underlying conductive layer at the bottom of the openings. A barrier layer is formed on the surface of the substrate. A portion of the barrier layer is removed at the bottom of the opening to expose the underlying conductive layer. A copper plug is formed in the opening such that the bottom of the plug is in contact with the exposed conductive layer. The substrate can be subjected to further processing if desired. The invention also includes a copper interconnect structure having increased resistance to electromigration.
    Type: Application
    Filed: October 12, 2004
    Publication date: March 24, 2005
    Inventors: Charles May, Wilbur Catabay
  • Patent number: 6239499
    Abstract: Provided is a method and composition for obtaining consistent alignment mark profiles with both detectibiliy and detection accuracy for use in conjunction with CMP planarization processes in semiconductor fabrication. The method involves physical vapor deposition of metal over an angled, metal-lined alignment mark trench in the surface of a semiconductor wafer following wafer planarization by CMP. The shape of the trench creates a shadowing effect which produces minimal deposition in the angled region of the trench and overcomes asymmetric metal loss due to attack from slurry accumulating in the trench during CMP. The result is the formation of a reliable and reproducible alignment mark.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: May 29, 2001
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Shumay X. Dou, Wilbur Catabay
  • Patent number: 6204550
    Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: March 20, 2001
    Assignee: LSI Logic Corporation
    Inventors: Zhihai Wang, Wei-Jen Hsia, Wilbur Catabay
  • Patent number: 5994211
    Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: November 30, 1999
    Assignee: LSI Logic Corporation
    Inventors: Zhihai Wang, Wei-Jen Hsia, Wilbur Catabay
  • Patent number: 5926720
    Abstract: Provided is a method and composition for obtaining consistent alignment mark profiles with both detectibiliy and detection accuracy for use in conjunction with CMP planarization processes in semiconductor fabrication. The method involves physical vapor deposition of metal over an angled, metal-lined alignment mark trench in the surface of a semiconductor wafer following wafer planarization by CMP. The shape of the trench creates a shadowing effect which produces minimal deposition in the angled region of the trench and overcomes asymmetric metal loss due to attack from slurry accumulating in the trench during CMP. The result is the formation of a reliable and reproducible alignment mark.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: July 20, 1999
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Wilbur Catabay, Shumay X. Dou