Patents by Inventor Wilfred Gomes

Wilfred Gomes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210074695
    Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.
    Type: Application
    Filed: December 28, 2017
    Publication date: March 11, 2021
    Inventors: Wilfred GOMES, Mark BOHR, Glenn J. HINTON, Rajesh KUMAR
  • Publication number: 20210013188
    Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.
    Type: Application
    Filed: September 28, 2017
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Sanka Ganesan, DOUG INGERLY, ROBERT SANKMAN, MARK BOHR, DEBENDRA MALLIK
  • Publication number: 20200312833
    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Applicant: INTEL CORPORATION
    Inventors: WILFRED GOMES, MARK T. BOHR, RAJESH KUMAR, ROBERT L. SANKMAN, RAVINDRANATH V. MAHAJAN, WESLEY D. MC CULLOUGH
  • Patent number: 10784204
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Wilfred Gomes, Yu Amos Zhang, Ram S. Viswanath, Rajasekaran Swaminathan, Sriram Srinivasan, Yidnekachew S. Mekonnen, Sanka Ganesan, Eduard Roytman, Mathew J. Manusharow
  • Publication number: 20200258759
    Abstract: Techniques and mechanisms for conducting heat with a packaged integrated circuit (IC) device. In an embodiment, the IC device comprises a package substrate and one or more IC dies coupled thereto, where a thermal conductor of the IC device extends through the package substrate. A thermal conductivity of the thermal conductor is more than 20 Watts per meter per degree Kelvin (W/mK). In another embodiment, thermal conductor further extends at least partially through a mold compound disposed on the one or more IC dies.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 13, 2020
    Inventors: Wilfred GOMES, Ravindranath V. MAHAJAN, Ram S. VISWANATH
  • Publication number: 20200258852
    Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 13, 2020
    Inventors: Wilfred GOMES, Mark BOHR, Doug INGERLY, Rajesh KUMAR, Harish KRISHNAMURTHY, Nachiket Venkappayya DESAI
  • Publication number: 20200211970
    Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Wilfred GOMES, Mark BOHR, Rajabali KODURI, Leonard NEIBERG, Altug KOKER, Swaminathan SIVAKUMAR
  • Patent number: 10685947
    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mark T. Bohr, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough
  • Publication number: 20200144186
    Abstract: A package substrate and a package assembly including a package substrate including a substrate body including a plurality of first contact points on a surface thereof configured for electrical connection to a first die and a plurality of second contact points on the surface configured for electrical connection to a second die; and a bridge coupled to the substrate body, the bridge including active device circuitry that is coupled to ones of the plurality of first contact points and ones of the plurality of second contact points. A method of forming a package assembly including coupling a first die to a package substrate, the package substrate including a bridge substrate including active device circuitry; and coupling a second die to the package substrate, wherein coupling the first die and the second die to the package substrate includes coupling the first die and the second die to the active circuitry.
    Type: Application
    Filed: September 13, 2017
    Publication date: May 7, 2020
    Inventors: Thomas P. THOMAS, Wilfred GOMES, Ravindranath V. MAHAJAN, Rajesh KUMAR, Mark T. BOHR, Dheeraj SUBBAREDDY, Ankireddy NALAMALPU, Mahesh KUMASHIKAR
  • Publication number: 20200066679
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Application
    Filed: December 21, 2017
    Publication date: February 27, 2020
    Inventors: Mark T. BOHR, Wilfred GOMES, Rajesh KUMAR, Pooya TADAYON, Doug INGERLY
  • Publication number: 20200066641
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Application
    Filed: July 2, 2016
    Publication date: February 27, 2020
    Inventors: Kemal AYGUN, Richard J. DISCHLER, Jeff C. MORRISS, Zhiguo QIAN, Wilfred GOMES, Yu Amos ZHANG, Ram S. VISWANATH, Rajasekaran SWAMINATHAN, Sriram SRINIVASAN, Yidnekachew S. MEKONNEN, Sanka GANESAN, Eduard ROYTMAN, Mathew J. MANUSHAROW
  • Publication number: 20200058646
    Abstract: Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mark Bohr, Brian S. Doyle
  • Publication number: 20190221556
    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Inventors: WILFRED GOMES, MARK T. BOHR, RAJESH KUMAR, ROBERT L. SANKMAN, RAVINDRANATH V. MAHAJAN, WESLEY D. MC CULLOUGH
  • Publication number: 20190206834
    Abstract: Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mark T. Bohr, Udi Sherel, Leonard M. Neiberg, Nevine Nassif, Wesley D. Mc Cullough
  • Publication number: 20190206798
    Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: ANDREW P. COLLINS, DIGVIJAY A. RAORANE, WILFRED GOMES, RAVINDRANATH V. MAHAJAN, SUJIT SHARAN
  • Publication number: 20040268032
    Abstract: According to one embodiment a content addressable memory (CAM) is disclosed. The CAM includes a memory array including a plurality of storage elements, a first read port, and a first set of bit compare components associated with the first read port and each of the plurality storage elements to compare bit data. Each of the first set of bit compare components are positioned separate from an associated storage element.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Badarinath N. Kommandur, Wilfred Gomes
  • Publication number: 20040123037
    Abstract: According to some embodiments, an interconnect structure includes write and read structures.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventors: Wilfred Gomes, Terry I. Chappell, Thomas D. Fletcher