Abstract: Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., ?25° C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.

Abstract: In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

Abstract: Thermoelectric (TE) devices and their manufacture on integrated circuit (IC) dies to improve thermal performance. An IC die may include a substrate with transistors on one side, a heat spreader on a second side, and a TE device between them. The TE device may have TE elements with similar dimensions as transistor features. An IC die with transistor circuitry blocks in multiple areas of an IC die may include TE devices between each of the transistor circuitry blocks and a heat spreader.

Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include thick hysteretic elements (i.e., hysteretic elements having a thickness of at least 10-15 nanometers, e.g., between 55 and 100 nanometers), and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate insulator having a thick hysteretic element and an interface layer, where the thick hysteretic element is between the interface layer and a gate electrode material, and the interface layer is between the thick hysteretic element and a channel material of a transistor. The interface layer may be a dielectric material with an effective dielectric constant of at least 20 and/or be a dielectric material that is thinner than about 3 nanometers. Such an interface layer may help improve gate control and allow use of thick hysteretic elements while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Reducing transistor dimensions at the gate allows keeping the footprint of the transistor relatively small and comparable to what could be achieved implementing a transistor with a shorter gate length while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

Abstract: Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.

Abstract: Memory devices including vertical transistors and methods of forming such memory devices are disclosed. An example memory device includes a substrate, a BL in the substrate, a channel region over a portion of the BL, a second region over the channel region, an insulator wrapped around at least a portion of the channel region, and a WL. The BL also operates as one of a source region and a drain region of the transistor. The second region is the other one of the source region and the drain region. The WL wraps around at least a portion of the insulator and is separated from the channel region by the insulator. In some embodiments, the BL is formed in a trench in the substrate. An aspect ratio of the BL is in a range from 0.5 to 10. The BL may have a higher conductivity than the channel region.

Abstract: Hybrid FETs and methods of forming such hybrid FETs are disclosed. An example hybrid FET includes a channel region, a first region, a second region, a third region, and two gates. A gate may wrap around a portion of the channel region. The channel region may be over a first substrate (e.g., a substrate on which the channel region is formed) but cross a second substrate. The channel region is shared by a MOSFET and a TFET. The first region and second region constitute the source and drain of the MOSFET and are doped with dopants of the same type. The first region and third region constitute the source and drain of the TFET and are doped with dopants of opposite types. The third region may be placed at the opposite side of the second substrate from the first region and the second region.

Abstract: IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

Abstract: IC devices including vertical TFETs are disclosed. An example IC device includes a substrate, a channel region, a first region, and a second region. One of the first and second regions is a source region and another one is a drain region. The first region includes a first semiconductor material. The second region includes a second semiconductor material that may be different from the first semiconductor material. The first region and the second region are doped with opposite types of dopants. The channel region includes a third semiconductor material that may be different from the first or second semiconductor material. The channel region is between the first region and the second region. The first region is between the channel region and the substrate. In some embodiments, the first or second region is formed through layer transfer or epitaxy (e.g., graphoepitaxy, chemical epitaxy, or a combination of both).

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Embodiments of the present disclosure are based on recognition that extending at least one of two S/D contacts of a transistor into a channel layer while keeping it separated from a corresponding gate stack by a channel material may allow keeping the footprint of the transistor relatively small while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower. For multiple transistors, some of the S/D contacts may be shared to further increase transistor density.

Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include dipole layers, and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate oxide having both a high-k dielectric and a dipole layer. In some embodiments, a thin dipole layer may directly border a channel material of choice and may be between the channel material and the high-k dielectric. In other embodiments, a passivation layer may spontaneously form between the dipole layer and the channel material. In still other embodiments, the high-k dielectric may be between the dipole layer and the channel material. Temporary polarization provided by the dipole layer may increase the effective dielectric constant of the high-k dielectric and may allow to use thinner high-k dielectrics and/or high-k dielectrics of suboptimal quality while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: Stitched dies having high bandwidth and capacity are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer, wherein the first device layer is a logic device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the first die by a scribe region. The second device layer is a transistor device layer, and the second plurality of metallization layers includes a layer of capacitor structures between an upper metallization layer portion and a lower metallization layer portion. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies.

Abstract: Stitched dies having backside power delivery are described are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A signal line is coupling the first die and the second die at a first side of the first and second dies. A backside power rail is coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side.

Abstract: Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.