Patents by Inventor Willem Zwart

Willem Zwart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180176034
    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
    Type: Application
    Filed: February 19, 2018
    Publication date: June 21, 2018
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Willem ZWART, John Bruce BOWLERWELL, Michael PAGE, Alastair BOOMER
  • Patent number: 9946672
    Abstract: A method of transferring control data between a master device and a slave device over a path including at least one intermediate device, such that the path includes multiple path segments between successive pairs of devices. Data is transferred on each path segment in a plurality of frames of data, wherein the frames are synchronized between said path segments. The control data is transmitted in command slots of each frame, wherein a command slot comprises a set of control data bit slots, and wherein a control data bit slot is a time window associated with the transfer of a single control data bit over a single path segment between the devices on the path segment.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 17, 2018
    Assignee: Cirrus Logic, Inc.
    Inventor: Willem Zwart
  • Publication number: 20180102894
    Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 12, 2018
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventor: Willem ZWART
  • Patent number: 9935786
    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: April 3, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Willem Zwart, John Bruce Bowlerwell, Michael Page, Alastair Boomer
  • Publication number: 20180067715
    Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronisation data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronisation data pattern comprises first signal level transitions on the at least one wire, synchronised to a master transmission clock. At second times, a second synchronisation data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronisation data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventor: Willem ZWART
  • Patent number: 9900143
    Abstract: A method is used for transferring data over a half-duplex wired communications link, wherein the wired communications link comprises first and second wires. The method comprises, in each of a plurality of frames: transferring a clock signal on the first wire in a first direction; transferring first payload data on the second wire in the first direction; transferring second payload data on the second wire in a second direction opposite to the first direction; and transferring control data on the second wire, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 20, 2018
    Assignee: Cirrus Logic, Inc.
    Inventor: Willem Zwart
  • Patent number: 9875197
    Abstract: A method is provided for use in a host module, for identifying at least one accessory module on a bus, wherein the bus is configured to allow multiple accessory modules to be connected to the host module. The method includes sending a query to any accessory module connected to the bus, the query concerning whether the or each accessory module meets a specified criterion; and receiving synchronized responses from any accessory module that meets the specified criterion connected to the bus where said responses are specific to the query but non-specific to an effectively uniquely distinguishing feature of the individual module. It is then possible to determine from redundant information contained in an aggregate of the synchronized responses whether there is (a) no accessory module meeting the specified criterion, or (b) at least one accessory module meeting the specified criterion.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 23, 2018
    Assignee: Cirrus Logic, Inc.
    Inventor: Willem Zwart
  • Patent number: 9853804
    Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 26, 2017
    Assignee: Cirrus Logic, Inc.
    Inventor: Willem Zwart
  • Patent number: 9836274
    Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronization data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronization data pattern comprises first signal level transitions on the at least one wire, synchronized to a master transmission clock. At second times, a second synchronization data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronization data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 5, 2017
    Assignee: Cirrus Logic, Inc.
    Inventor: Willem Zwart
  • Publication number: 20170060794
    Abstract: A method of transferring control data between a master device and a slave device over a path including at least one intermediate device, such that the path includes multiple path segments between successive pairs of devices. Data is transferred on each path segment in a plurality of frames of data, wherein the frames are synchronized between said path segments. The control data is transmitted in command slots of each frame, wherein a command slot comprises a set of control data bit slots, and wherein a control data bit slot is a time window associated with the transfer of a single control data bit over a single path segment between the devices on the path segment.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 2, 2017
    Inventor: Willem Zwart
  • Publication number: 20170019244
    Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.
    Type: Application
    Filed: October 30, 2015
    Publication date: January 19, 2017
    Inventor: Willem Zwart
  • Publication number: 20160344536
    Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 24, 2016
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Bhoodev Kumar, Muraleedharan Ramakrishnan, Vivek Oppula, Thomas Hoff, Willem Zwart
  • Publication number: 20160335211
    Abstract: An audio system comprises a master device; a slave device; and a wired connection, suitable for connecting the master device and the slave device, and having at least two wires.
    Type: Application
    Filed: October 30, 2015
    Publication date: November 17, 2016
    Inventor: Willem Zwart
  • Publication number: 20160337113
    Abstract: A method is used for transferring data over a half-duplex wired communications link, wherein the wired communications link comprises first and second wires. The method comprises, in each of a plurality of frames: transferring a clock signal on the first wire in a first direction; transferring first payload data on the second wire in the first direction; transferring second payload data on the second wire in a second direction opposite to the first direction; and transferring control data on the second wire, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.
    Type: Application
    Filed: October 30, 2015
    Publication date: November 17, 2016
    Inventor: Willem Zwart
  • Publication number: 20160267028
    Abstract: A method is provided for use in a host module, for identifying at least one accessory module on a bus, wherein the bus is configured to allow multiple accessory modules to be connected to the host module. The method includes sending a query to any accessory module connected to the bus, the query concerning whether the or each accessory module meets a specified criterion; and receiving synchronised responses from any accessory module that meets the specified criterion connected to the bus where said responses are specific to the query but non-specific to an effectively uniquely distinguishing feature of the individual module. It is then possible to determine from redundant information contained in an aggregate of the synchronised responses whether there is (a) no accessory module meeting the specified criterion, or (b) at least one accessory module meeting the specified criterion.
    Type: Application
    Filed: March 8, 2016
    Publication date: September 15, 2016
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventor: Willem ZWART
  • Publication number: 20160269193
    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 15, 2016
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Willem ZWART, John Bruce BOWLERWELL, Michael PAGE, Alastair BOOMER
  • Publication number: 20160269201
    Abstract: A system comprises a first module and a second module, connected by a transmission line comprising first and second wires. The first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires. The first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has first data to transmit. The second module includes current generation circuitry, for generating a signal current in response to second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has second data to transmit. The first module includes respective resistances connected to the first and second wires.
    Type: Application
    Filed: October 30, 2015
    Publication date: September 15, 2016
    Inventors: Willem Zwart, Bhupendra Singh Manola
  • Publication number: 20160159800
    Abstract: The present invention relates to compounds of general Formula I or a pharmaceutically acceptable salt thereof. The compounds can be used in the treatment of immune, autoimmune, inflammatory diseases, cardiovascular diseases, infectious diseases, bone resorption disorders, neurodegenerative diseases or proliferative diseases.
    Type: Application
    Filed: July 9, 2015
    Publication date: June 9, 2016
    Inventors: Tjeerd Andries Barf, Arthur Oubrie, Carsten Schultz-Fademrecht, Eduard Willem Zwart, Niels Hoogenboom, Sander Martijn De Wilde, Allard Kaptein
  • Publication number: 20160154622
    Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronisation data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronisation data pattern comprises first signal level transitions on the at least one wire, synchronised to a master transmission clock. At second times, a second synchronisation data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronisation data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory.
    Type: Application
    Filed: October 30, 2015
    Publication date: June 2, 2016
    Inventor: Willem Zwart
  • Patent number: 9102676
    Abstract: The present invention relates to compounds of general Formula (I) or a pharmaceutically acceptable salt thereof. The compounds can be used in the treatment of immune, autoimmune, inflammatory diseases, cardiovascular diseases, infectious diseases, bone resorption disorders, neurodegenerative diseases or proliferative diseases.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: August 11, 2015
    Assignee: Merck Sharp & Dohme B.V.
    Inventors: Tjeerd Andries Barf, Arthur Oubrie, Carsten Schultz-Fadermrecht, Eduard Willem Zwart, Niels Hoogenboom, Sander Martijn De Wilde, Allard Kaptein