Abstract: A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).

Abstract: A multiprocessor computer system comprises a plurality of processing element nodes and an interconnect network interconnecting the plurality of processing element nodes. An interface circuit is associated with each one of the plurality of processing element nodes. The interface circuit has a lookup table having n-number of routing entries for a given destination node. Each one of the n-number of routing entries associated with a different class of traffic. The network traffic is routed according to the class.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.

Abstract: A memory device and method which provide at least one memory segment. The memory segment includes at least one first portion which is configured to store data. The memory segment also includes at least one second portion associated with the first portion, and which is configured to store directory information for at least one cache line thereon.

Abstract: A boot binding that is easily and quickly rotatable between different positions is disclosed. In one embodiment of the invention, a boot binding comprises a rotatable boot attachment member and an intermediate locking arrangement that holds the boot attachment member in an intermediate position. A force applied to the boot attachment member releases the intermediate locking arrangement such that the boot attachment member can be moved from its intermediate position to a different position.

Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.

Abstract: A boot binding that is easily and quickly rotatable between different positions is disclosed. In one embodiment of the invention, a boot binding comprises a rotatable boot attachment member and an intermediate locking arrangement that holds the boot attachment member in an intermediate position. A force applied to the boot attachment member releases the intermediate locking arrangement such that the boot attachment member can be moved from its intermediate position to a different position.

Abstract: Methods for testing a [A] tape carrier package (TCP) for an integrated circuit device that includes two sets of test pads. A first set of test pads are located along the outer edges of the TCP and are used to test the performance of the integrated circuit device once the TCP has been fabricated and assembled. A second set of test pads is also provided between the TCP outer leads and integrated circuit device for testing the performance of the device once the TCP has been removed from a printed circuit board.

Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.

Abstract: A polymer-dispersed liquid crystal device comprises a multiplicity of droplets of a birefringent, functionally nematic liquid crystal material dispersed in a matrix comprising the reaction product of ultraviolet radiation polymerizable materials. The device specularly transmits incident light as a function of the magnitude of an electric field applied across the device. The difference between a first applied voltage corresponding to a first percentage of the total incident light transmitted by the device as specular light and a second applied voltage corresponding to a second percentage of the total incident light transmitted by the device as specular light is greater than or equal to 15 volts. As a result, a polymer-dispersed liquid crystal device according to the invention displays a variable grey scale which has a uniform optical transmission. A method for preparing a PDLC device in general is also disclosed.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.

Abstract: A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.

Abstract: The present invention relates to an X-ray intensifying screen comprising a support, a fluorescent layer coated thereon which comprises fluorescent phosphor particles dispersed in a binder, and a protective top-coat layer covering said fluorescent layer, characterized in that at least one of said fluorescent and top-coat layers comprises at least one salt selected from the group consisting of fluoroalkylsulfonyl methides, fluoroalkylsulfonyl imides, and fluoroalkylsulfonyl amides.

Abstract: The computer system having a first circuit board with a processor for processing information and a slot for receiving an IC card. The slot includes multiple pins for connection to the IC card. The IC card includes a second processor coupled to a second circuit board, where the processor is contained within outer framing structure. An interface coupled to the circuit board may be coupled to the multiple pins in the slot, such that the second processor in the integrated circuit card is able to control the computer system.

Abstract: A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline.

Abstract: The present invention relates to a silver halide photographic material comprising a support, at least one silver halide emulsion layer coated thereon, and a hydrophilic colloid layer coated on said at least one silver halide emulsion layer, wherein said hydrophilic colloid layer comprises a combination of (a) at least one surfactant selected from the group consisting of non-ionic perfluoroalkyl(ene)polyoxyethylene surfactants and polyoxyethylene-modified polysiloxane surfactants, and (b) at least one salt of perfluoroalkylsulfonyl imide or perfluoroalkylsulfonyl methide.

Abstract: A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

Abstract: A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.

Abstract: A mechanism for dividing an integer dividend by an integer divisor to generate an integer quotient operates by aligning the divisor relative to the dividend such that a right-most bit of the divisor is aligned with a bit M of the dividend. The divisor is compared to an integer value whose right-most bits are equal to bits of the dividend which are aligned with bits of the divisor. As a result of this comparison, quotient bits which positionally correspond to the dividend bit M and to bits of the dividend which are located to the left of the dividend bit M are cleared to zero. Also as a result of the comparison, the dividend is divided by the divisor as aligned relative to the dividend to thereby generate values for any uncleared quotient bits.

Abstract: The crosslinking of an antistatic polymer and crossliking agent on a flexible polymer abstract is enhanced by wrapping of the antistatic coated polymer substrate and heating said wrapped substrate to crosslink the coating.