Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

Abstract: A mandrel (2) comprising a body portion (4) having an outer surface for receiving a stretchable closed wrapper (20), the mandrel having an end (6) adapted for mounting on a self supporting object (18) to be wrapped such that the wrapper can be slid over the mandrel and delivered therefrom onto the outer surface (22) of the object, in which the mandrel includes a portion which engages with the object to allow the mandrel to seat on an end of the object.

Abstract: A method of analyzing characteristics of a subterranean formation includes transmitting a signal at least partially into a material of the subterranean formation such that the signal is transformed in a manner indicative of a characteristic of the material, receiving the transformed signal from the material, converting the transformed signal into image data indicative of the characteristic of the material, applying a first set of machine executable rules to the image data to produce segmented image data, wherein portions of the image that are sufficiently related according to the applied rules are grouped into segments, and analyzing, according to a second set of machine executable rules, the segmented image data to produce a geological profile of the subterranean formation.

Abstract: A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: A temperature control apparatus is suitable for use in devices such as consumer electronics devices having different thermal characteristics. According to an exemplary embodiment, the temperature control apparatus includes a fan having a field winding (F3) and a speed controller for providing a speed control signal to the field winding (F3) responsive to a first control signal to control a rotating speed of the fan. First and second terminals of the fan enable operating power to be provided to the field winding (F3) and the speed controller. At least one of the first and second terminals is operatively coupled to a first voltage source. A third terminal of the fan provides the first control signal to the speed controller, and is operatively coupled to a second voltage source.

Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract: A gripper 1 comprising a support 5, 6 for attachment to a robotic arm, outer gripping plates 2, 3 mounted for movement on the support, drive means 13, 14, 15 for independently moving the outer plates 2 and 3 with respect to an intermediate gripping plate 4 mounted for pivotal movement towards and away from the outer plates 2, 3, the arrangement allowing for separate articles or groups of articles to be gripped between each of the outer plates 2, 3 and the intermediate plate 4 to increase the capacity of the gripper 1.

Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry.

Abstract: An apparatus for coating surfaces of a workpiece configured to establish a pressure gradient within internal passageways through the workpiece, so that the coating within the internal passageways exhibits intended characteristics, such as those relating to smoothness or hardness. The coating apparatus may include any or all of a number of cooperative systems, including a plasma generation system, a manipulable workpiece support system, an ionization excitation system configured to increase ionization within or around the workpiece, a biasing system for applying a selected voltage pattern to the workpiece, and a two-chamber system that enables the plasma generation to take place at a first selected pressure and the deposition to occur at a second selected pressure.

Abstract: A device for use in monitoring a swab method, the device includes a first substrate substantially adjacent a second substrate, the first substrate and the second substrate having disposed therebetween a test material.

Abstract: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

Abstract: An apparatus and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.