Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: A radiation detecting system including a radiation detecting section having one or more radiation detecting circuits and a circuit adjustment section for adjusting other circuitry to be protected. Radiation detecting circuits are provided to detect a pulse of radiation and/or a total radiation dose accumulation.

Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low &kgr; nanopore/nanofoam dielectric material adjacent the conductive line ends.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A programmable device including: an antifuse; a resistive heating element having a substantially temperature to power response, the resistive heating element adjacent to but not in contact with the antifuse; and means for passing an electric current through the resistive heating element in order to generate heat to raise the temperature of the antifuse sufficiently high enough to decrease a programming voltage of the antifuse, a time the programming voltage is applied to the antifuse or both the programming voltage of the antifuse and the time the programming voltage is applied to the antifuse.

Abstract: The present invention relates to an alignment mark structure for laser fusing. An alignment mark structure is formed which is comprised of image elements that are placed on different film layers in a semiconductor device. Alignment is accomplished by examining the difference in reflected energy of a laser beam as the beam traverses the alignment mark structure. By forming the alignment mark structure such that it has elements on different film layers, the reflected energy can be modulated to avoid the situation in which no difference in reflected energy is found, which would make the alignment mark invisible to the laser fusing tool. A method of applying the alignment mark structure is also disclosed.

Abstract: An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).

Abstract: An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

Abstract: A solid-state CCD device suitable for forming into arrays and for use with suitable hardware to form video image capture devices and methods for fabricating same are provided.

Abstract: An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

Abstract: Increased pixel density and increased sensitivity to blue light are provided in a charge couple device employing sidewall and surface gates.

Abstract: An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.