Abstract: Some embodiments of the inventive subject matter are directed to determining that a memory access request results in a cache miss and determining an amount of cache resources used to service cache misses within a past period in response to determining that the memory access request results in the cache miss. Some embodiments are further directed to determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed a threshold. In some embodiments, the threshold corresponds to reservation of a given amount of cache resources for potential cache hits. Some embodiments are further directed to rejecting the memory access request in response to the determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed the threshold.

Abstract: Some embodiments of the inventive subject matter are directed to a cache comprising a tracking unit and cache state machines. In some embodiments, the tracking unit is configured to track an amount of cache resources used to service cache misses within a past period. In some embodiments, each of the cache state machines is configured to, determine whether a memory access request results in a cache miss or cache hit, and in response to a cache miss for a memory access request, query the tracking unit for the amount of cache resources used to service cache misses within the past period. In some embodiments, the each of the cache state machines is configured to service the memory access request based, at least in part, on the amount of cache resources used to service the cache misses within the past period according to the tracking unit.

Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

Abstract: According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.

Abstract: According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.

Abstract: An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.

Abstract: Handling requests for power reduction by first enabling a request for an amount of power change, e.g. reduction by any partition. In response to the request for power reduction, an equal proportion of the whole amount of power reduction is distributed between each of a set of cores providing the entitlements to the partitions, and the entitlement of the requesting partition is reduced by an amount corresponding to the whole amount of the power change.

Abstract: A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.

Abstract: According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.

Abstract: A method, data processing system, and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

Abstract: A system and technique for managing rollback in a transactional memory environment is disclosed. The system includes a processor, a transactional memory, and a transactional memory manager (TMM) configured to perform a rollback on the transactional memory. The TMM is configured to, responsive to detecting a begin transaction directive by the processor, detect an access of a first memory location of the transactional memory not needing rollback and indicate that the first memory location does not need to be rolled back while detecting an access to a second memory location of the transactional memory and indicating that a rollback will be required. The TMM is also configured to, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omit a rollback of the first memory location while performing rollback on the second memory location.

Abstract: Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.

Abstract: Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

Abstract: A computer implemented method includes determining first characteristics of a first logical partition, the first characteristics including a memory footprint characteristic. The method includes assigning a first portion of a first set of physical computing resources to the first logical partition. The first set of physical computing resources includes a plurality of processors that includes a first processor having a first processor type and a second processor having a second processor type. The first portion includes the second processor. The method includes dispatching the first logical partition to execute using the first portion. The method includes creating a second logical partition that includes the second processor and assigning a second portion of the first set of physical computing resources to the second logical partition. The method includes dispatching the second logical partition to execute using the second portion.

Abstract: A method, system and computer program product enables the granular collection and utilization of hardware statistical samples for the efficient scheduling and allocation of data processing resources. In particular, a Partition Statistics Capture and Analysis (PSCA) utility utilizes special purpose registers to collect statistical samples, such as: (1) instructions completed; (2) Level2 (L2) cache misses; (3) cycles per instruction (CPI); and/or (4) other statistics selected based on the programming of the PSCA utility. Further, these statistical samples are utilized for the several purposes, including: (1) determining how long (time) the footprint of a partition takes to become established during the “cold start” period, i.e., during system instantiation; (2) detecting movement of the CPI curve in order to determine the (shifted) location of the onset of steady state (i.e., the knee) on the CPI curve; and (3) utilizing the statistical samples to guide dispatch decisions and make tuning recommendations.

Abstract: According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.

Abstract: A hybrid CPU system wherein the plurality of processors forming the hybrid system are initially undifferentiated by type or class. Responsive to the sampling of the threads of a received and loaded computer application to be executed, the function of at least one of the processors is changed so that the threads of the sampled application may be most effectively processed/run on the hybrid system.

Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

Abstract: A method, apparatus, and computer program product for running software on an adapter. In response to a connection of a hardware interface for the adapter with a current host computer, a processor unit in the adapter determines whether a set of protocols for communicating with the current host computer to access resources is present on the adapter. In response to the set of protocols being absent on the adapter, the processor unit obtains the set of protocols from the current host computer. The processor unit identifies a set of available resources in the current host computer for use by the adapter using the set of protocols. The processor unit runs software stored on a set of storage devices in the adapter using the set of available resources identified for use by the adapter.

Abstract: Handling requests for power reduction by first enabling a request for an amount of power change, e.g. reduction by any partition. In response to the request for power reduction, an equal proportion of the whole amount of power reduction is distributed between each of a set of cores providing the entitlements to the partitions, and the entitlement of the requesting partition is reduced by an amount corresponding to the whole amount of the power change.