Patents by Inventor William A. Maron
William A. Maron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110161979Abstract: Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicant: International Business Machines CorporationInventors: Diane G. Flemming, William A. Maron, Ram Raghavan, Satya Prakash Sharma, Mysore S. Srinivas
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Publication number: 20110145505Abstract: Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vaijayanthimala K. Anand, Diane G. Flemming, William A. Maron, Mysore S. Srinivas
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Patent number: 7962677Abstract: A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable.Type: GrantFiled: July 15, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: William A. Maron, Diane Garza Flemming, Ghadir Robert Gholami, Mysore Sathyanarayana Srinivas, Octavian Florin Herescu
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Publication number: 20110107031Abstract: A method, programmed medium and system are provided for enabling a core's cache capacity to be increased by using the caches of the disabled or non-enabled cores on the same chip. Caches of disabled or non-enabled cores on a chip are made accessible to store cachelines for those chip cores that have been enabled, thereby extending cache capacity of enabled cores.Type: ApplicationFiled: November 5, 2009Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vaijayanthimala K. Anand, Diane Garza Flemming, William A. Maron, Mysore Sathyanarayana Srinivas
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Publication number: 20110093861Abstract: A data processing system includes physical computing resources that include a plurality of processors. The plurality of processors include a first processor having a first processor type and a second processor having a second processor type that is different than the first processor type. The data processing system also includes a resource manager to assign portions of the physical computing resources to be used when executing logical partitions. The resource manager is configured to assign a first portion of the physical computing resources to a logical partition, to determine characteristics of the logical partition, the characteristics including a memory footprint characteristic, to assign a second portion of the physical computing resources based on the characteristics of the logical partition, and to dispatch the logical partition to execute using the second portion of the physical computing resources.Type: ApplicationFiled: October 21, 2009Publication date: April 21, 2011Applicant: International Business Machines CorporationInventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Publication number: 20110022803Abstract: An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.Type: ApplicationFiled: July 24, 2009Publication date: January 27, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diane Garza Flemming, William A. Maron, Ram Raghavan, Mysore Sathyanarayana Srinivas, Basu Vaidyanathan
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Publication number: 20100275206Abstract: Standalone software performance optimizer systems for hybrid systems include a hybrid system having a plurality of processors, memory operably connected to the processors, an operating system including a dispatcher loaded into the memory, a multithreaded application read into the memory, and a static performance analysis program loaded into the memory; wherein the static performance analysis program instructs at least one processor to perform static performance analysis on each of the threads, the static performance analysis program instructs at least one processor to assign each thread to a CPU class based on the static performance analysis, and the static performance analysis program instructs at least one processor to store each thread's CPU class.Type: ApplicationFiled: April 22, 2009Publication date: October 28, 2010Applicant: International Business Machines CorporationInventors: Greg Mewhinney, Diane Flemming, David Whitworth, William Maron, Mysore Srinivas
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Publication number: 20100180089Abstract: A method, system, and computer usable program product for managing thermal condition of a memory are provided in the illustrative embodiments. A condition that a threshold value of a thermal condition of the memory has been exceeded or is likely to be exceeded is identified. A portion of a first workload is identified as being a cause of exceeding the threshold. A second portion of a second workload is identified, the second portion not causing the threshold to be exceeded when executed. A set of operations corresponding to the first portion is interleaved with a second set of operations corresponding to the second portion. The interleaved first and second portions of the first and second workloads are executed, causing the thermal condition of the memory to remain below the threshold. The second portion may use a second memory, a second area of the memory, or a combination thereof when executing.Type: ApplicationFiled: January 14, 2009Publication date: July 15, 2010Applicant: International Business Machines CorporationInventors: Diana Garza Flemming, Ghadir Robert Gholami, Octavian Florin Herescu, William A. Maron, Mysore Sathyanarayana Srinivas
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Patent number: 7711905Abstract: A system for managing data in a plurality of storage locations. In response to a least recently used algorithm wanting to move data from a cache to a storage location, an aging table is searched for an associated entry for the data. In response to finding the associated entry for the data in the aging table, an indicator is enabled on the data. In response to determining that the indicator is enabled on the data, the data is kept in the cache despite the least recently used algorithm wanting to move the data to the storage location.Type: GrantFiled: July 16, 2007Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Diane Garza Flemming, Octavian Florin Herescu, William A. Maron, Mysore Sathyanarayana Srinivas
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Patent number: 7698530Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.Type: GrantFiled: March 28, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Patent number: 7698531Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.Type: GrantFiled: March 28, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Publication number: 20100017551Abstract: A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable.Type: ApplicationFiled: July 15, 2008Publication date: January 21, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William A. Maron, Diane Garza Flemming, Ghadir Robert Gholami, Mysore Sathyanarayana Srinivas, Octavian Florin Herescu
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Patent number: 7640400Abstract: A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory.Type: GrantFiled: April 10, 2007Date of Patent: December 29, 2009Assignee: International Business Machines CorporationInventors: William A. Maron, Greg R. Mewhinney, Mysore S. Srinivas, David B. Whitworth
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Patent number: 7617375Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.Type: GrantFiled: March 28, 2007Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Publication number: 20090252057Abstract: A method and system for replacing physical connections within a large enterprise system with wireless connections. A first wireless transceiver is associated with a node, wherein the node comprises one or more system service processors. A second wireless transceiver is associated with a main system service processor. System service processors associated with the node, referred to as node service processors, are assigned a unique identification (ID), e.g., a name and/or number, to identify the node service processors during wireless connection. An Ethernet cable is utilized to connect the node service processors to the main system service processor. The unique identification is transferred from the main system service processor to the node service processor, and then the Ethernet cable is disconnected. When the Ethernet cable is disconnected, the node service processor(s) communicate with the main system service processor via a wireless network utilizing the transceivers and unique IDs.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventors: DIANE G. FLEMMING, Ghadir R. Gholami, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
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Publication number: 20090138911Abstract: A method, medium and implementing processing system, are provided in which premium programming content is included in a standard program broadcasting system. The added content is stored at a user site for subsequent viewing at the user's convenience. The receipt and storing of the premium programming is accomplished without interfering with the receipt of standard broadcast signals. The premium programming, in one example, is transmitted and incrementally received and stored on a user's system even while standard programming is received and viewed by the user. When all of the broadcast increments of a premium program have been received and the premium program has been stored in the user's system, a signal is provided to the user to indicate the availability of the premium program for selective viewing by the user.Type: ApplicationFiled: November 27, 2007Publication date: May 28, 2009Inventors: Diane Garza Flemming, Ghadir Robert Gholami, Octavian Florin Herescu, William A. Maron, Mysore Sathyanarayana Srinivas
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Patent number: 7512837Abstract: A method for recovering lost cache capacity in a multi core chip having at least one defective core including identifying the cores contained in the chip that are viable cores and identifying at least one core contained in the chip that is defective. The method also includes identifying the cache memory local to the defective core and determining a redistribution of the cache resources local to the at least one defective core among the viable cores. The method also features dividing the cache memory local to the at least one defective core according to the redistribution determination and determining the address information associated with the cache memory local to the at least one defective core. The method also features providing the address information associated with the cache memory associated with the defective core to at least one of the viable cores, facilitating the supplementation of the cache memory local to the viable cores with the cache memory associated with the defective core.Type: GrantFiled: April 4, 2008Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Diane Flemming, Ghadier R. Gholami, Octavian F. Herescu, William A. Maron, Mysore M. Srinivas
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Publication number: 20090024800Abstract: A system for managing data in a plurality of storage locations. In response to a least recently used algorithm wanting to move data from a cache to a storage location, an aging table is searched for an associated entry for the data. In response to finding the associated entry for the data in the aging table, an indicator is enabled on the data. In response to determining that the indicator is enabled on the data, the data is kept in the cache despite the least recently used algorithm wanting to move the data to the storage location.Type: ApplicationFiled: July 16, 2007Publication date: January 22, 2009Inventors: Diane Garza Flemming, Octavian Florin Herescu, William A. Maron, Mysore Sathyanarayana Srinivas
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Publication number: 20080256302Abstract: A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Inventors: William A. Maron, Greg R. Mewhinney, Mysore S. Srinivas, David B. Whitworth
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Publication number: 20080244214Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas