Abstract: A method and apparatus for assigning a permanent identifier to a client node initially having a default identifier and being operably connected to a network. A server determines a location of the client node and assigns the permanent identifier to the client node in response to the location of the client node on the network.

Abstract: An underground horizontal boring apparatus includes a framework having a pair of guide tracks and a carriage connected to the framework for movement along the tracks. The apparatus includes a mechanism for moving the carriage in forward or backward directions along the guide tracks. A drill assembly is mounted to the carriage having a drill motor for rotation of a drill rod releasably coupled thereto. A clamp assembly is mounted to one end of the framework and includes a clamp for selectively gripping the drill rod so as to rotatably release the drill rod from the drill motor when the drill motor is operated in a reverse direction. Upon release, the carriage may be moved to a start position, another drill rod may be attached to the drill motor and first rod, and boring resumed.

Abstract: The present invention is directed to facilitating communication within an automation system having a plurality of networks and network protocols. Specifically, a Modbus network is operably connected to a network. A fieldbus coupler operably connected to both networks having a program facilitates communication within the automation system wherein devices connected to the network can be accessed for monitoring and/or controlling via Modbus commands. The fieldbus coupler (FBC) program accepts a Modbus function code containing one or more embedded message of varying types. The FBC program using additional information contained in the Modbus function code and the message type reads or writes only the required information to and from the field devices. This specific read or write request of the information and the embedding of more than one message type reduces overhead and bandwidth usage, thus improving bus response time and efficiency.

Abstract: A system and method for a mixer circuit places the RF and mixer core LO transistors on the same level in anti-series. The mixer circuit provides increased headroom, excellent linearity, controllable conversion-gain, and operates with a reduced supply voltage requirement.

Abstract: A method for optimizing communication in a network involving wanted and unwanted network messages wherein a set of filters are configured to accept all wanted network messages and minimize the acceptance of unwanted messages in accordance with a selection criteria. A first filter is configured to receive all wanted messages. The first filter includes a defined bit and an undefined bit. Each defined bit is either in a first state or in a second state. A second filter is set equal to the first filter. The first filter and the second filter compose a first set of filters. Potential configurations of the first set of filters are determined wherein each potential configuration is capable of accepting all wanted network messages. The potential configurations are optimized wherein the optimized configuration ensures acceptance of all wanted messages and reduces the amount of accepted unwanted messages.

Abstract: A method and apparatus for assigning a permanent identifier to a client node initially having a default identifier and being operably connected to a network. A server determines a location of the client node and assigns the permanent identifier to the client node in response to the location of the client node on the network.

Abstract: A method and apparatus for improving communication throughout a network is disclosed. The network includes a module capable of transmitting messages in response to a change of state. Bit errors transmitted within network are detected and a detected bit error rate is calculated. A residual, i.e., undetected, error probability is determined in response to the detected bit error rate. Corrective action towards reducing the effects of the residual errors is taken, e.g., retransmission of messages, in response to the residual error probability exceeding a predetermined threshold.

Abstract: A CANOpen network including a bus master and an I/O module are disclosed. Each are communicatively coupled to a common bus. The I/O module is subject to a state change. The bus master collects state information from the I/O module by sending a state signal from the I/O module to the bus master in response to a state change of the I/O module, sending a trigger signal from the bus master to the I/O module, and sending a state signal from the I/O module to the bus master in response to the trigger signal.

Abstract: A CANOpen network including a bus master and an I/O module is disclosed. Each is communicatively coupled to a common bus. The I/O module is subject to a state change. The bus master collects state information from the I/O module by determining if the bus master is prepared to receive further data from the bus and sending a trigger signal from the bus master to the I/O module if the bus master is prepared to receive further data from the bus. The I/O modules sends a state signal to the bus master in response to the trigger signal.

Abstract: According to a broad aspect of the invention, an apparatus (34) for decoding a Manchester encoded data stream is provided. The apparatus includes a transition detector (45) for receiving the Manchester encoded data stream to produce a transition indicating output when a transition of the Manchester encoded data stream is detected. Also, a circuit (105) is provided to generate an output control pulse a predetermined time after the transition indicating output is produced. A sampling flip-flop (120) receives the Manchester encoded data stream, and is controlled by the output control pulse to output a state of the Manchester encoded data to an output control circuit (125) when the output control pulse is generated. In a preferred embodiment, the sampling flip-flop (125) operates to generate a binary NRZ form of the Manchester encoded data stream.

Abstract: A monolithic digital chirp synthesizer (DCS) chip using GaAs/AlGaAs HI.sup.2 L technology. The 6500 HBT gate DCS chip is capable of producing linear frequency modulated (chirp) waveforms or single frequency waveforms. The major components of the DCS are two pipelined accumulators, a sine ROM, a cosine ROM and two digital to analog converters.

Abstract: A digital to analog converter and method for conversion is provided that includes an R-2R resistor ladder network formed with a plurality of current bit switches in a GaAs HI.sup.2 L integrated circuit. Each bit switch and R-2R node in the ladder network is associated with a corresponding bit position in the binary signal input to the converter. An arrangement of bipolar transistors (Q1, Q4) and diodes (D2-D3) is included in each bit switch (100) that steers current through one of two alternate paths, based on the logic state of the binary input signal (i e., "high" or "low" state). For one logic state of the binary input signal, current flows through the switch from the output of the digital to analog converter (110). For the alternate signal state, current flow from the output of the digital to analog converter is blocked. Therefore, each bit switch (100) operates as a single-pole-double-throw current mode switch under the control of the binary input signal (Ai).

Abstract: A method and apparatus is provided for accurate digital to analog conversion in which bipolar voltage switches are used in a GaAs I.sup.2 L integrated circuit. An architecture is provided that includes an R-2R resistor ladder network formed in a GaAs I.sup.2 L integrated circuit. A compound transistor pair (Q1, Q2) is connected to each leg (2R) of the ladder network in a digital to analog converter (110). Each transistor pair (Q1, Q2) is configured as a single-pole-double-throw voltage bit switch (100). The transistor pair switches the shunt (2R) resistors between two, alternative voltage levels (Vb, circuit "ground"), based on the state of the binary input logic signal (Ai). Each switch and respective leg in the ladder network relates to a corresponding bit position (Ai) in the input signal.

Abstract: A digital to analog converter (10) and method is provided in which a plurality of digital to analog converter cells (16) generate an analog output signal based on a digital input signal, the cells being characterized by a switching threshold. An error signal circuit (22) generates a control voltage signal for controlling a first variable delay register (12). Signals latched by the first variable delay register (12) are characterized by rising and falling edges, and the first variable delay register (12) is controlled by the control voltage signal such that the rising and falling edges cross the switching threshold at substantially the same time.

Abstract: A caulking tool of flat, square-shaped plastic having each of its four corners rounded to form four different radii. The caulking tool is used after caulking material is applied to create a compacted, smooth, uniform bead. It is unique in its method of use and the choice of four different radii offering four choices of bead size from one tool.

Abstract: A semiconductor chip for processing or storing information and a system comprising a plurality of semiconductor chips for processing or storing information. In one form of the invention each chip includes clock input and output circuitry for receiving and transmitting signals of a first frequency and transmission circuitry for receiving and transmitting data. The transmission circuitry is capable of sampling the data at a second clock frequency which is less than the first clock frequency. Circuit components are coupled to the clock circuitry and transmission circuitry for processing the data. In another form of the invention a semiconductor chip comprising clock input and output circuitry, transmission circuitry and circuit components for processing data further includes input circuitry for selecting a variable delay between the time data is received onto the chip and transmitted from the chipIn a preferred embodiment of the invention the semiconductor chip includes a memory array for storing data.

Abstract: A digital memory system of the type which includes an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell. A bit line pull-up transistor is positioned to function as a bit line current source and as a load device for the amplifier transistor. The amplifier transistor is connected between the pull-up transistor and the bit line and an output node positioned between the pull-up and amplifier transistors provides the amplified bit line signal corresponding to the state of a selected memory cell.

Abstract: A MESFET logic gate wherein a logic switch node is both a-c coupled to the output node, preferably by a capacitor network and is also separately DC coupled to it, preferably by a voltage level shifter circuit. The direct capacitative coupling increases the high-frequency cut-off frequency, and reduces the current requirement of the voltage level shifter circuit. The voltage level shifter circuit, even using small width devices, provides low frequency and DC response, so that circuits using the gate of the present invention do not require initialization and refresh cycle. Thus, both high speed and low power are attained.