Abstract: Disclosed herein is a composition having: a soft material having a shear modulus and a bulk modulus larger than the shear modulus and a plurality of encapsulated microbubbles within the soft material. The composition exhibits a discontinuous change in an acoustic property relative to an applied frequency. The composition may be used for wearable sensors, micromachines, medical devices, and metamaterials.

Abstract: An article having: an elastomeric jacket; a gel within the jacket; and a plurality of gas-filled, polymerically-encapsulated microbubbles suspended in the gel. The microbubbles have a Gaussian particle size distribution. The largest microbubble has a diameter at least 10 times the diameter of the smallest microbubble. The article may exhibit Anderson localization at at least one frequency of sound waves impacting the article.

Abstract: An article having: an elastomeric jacket; a gel within the jacket; and a plurality of gas-filled, polymerically-encapsulated microbubbles suspended in the gel. The microbubbles have a Gaussian particle size distribution. The largest microbubble has a diameter at least 10 times the diameter of the smallest microbubble. The article may exhibit Anderson localization at at least one frequency of sound waves impacting the article.

Abstract: Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.

Abstract: An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Abstract: An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Abstract: Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sample an incoming signal. A reference signal, such as a Nyquist signal, is applied to a data input of each of the latches. Statistics of “early” and “late” corrections applied to at least one of the clocks by a bang-bang phase detector in the clock and data recovery system are evaluated and a delay of a clock buffer associated with the at least one clock is adjusted to obtain approximately a 50% early-to-late ratio for the at least one clock. The clock and data recovery system ensures that the early-to-late ratio for the sum of the plurality of clocks is approximately 50%.

Abstract: A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.

Abstract: A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.

Abstract: Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage.

Abstract: Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide differential latch circuits. Such differential latch circuits include an input stage and a latch stage. The input stage provides an interim output that is available during a defined period, and the latch stage is operable to latch the temporary interim output during the defined period using a common clock.

Abstract: Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.

Abstract: Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.

Abstract: Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide differential latch circuits. Such differential latch circuits include an input stage and a latch stage. The input stage provides an interim output that is available during a defined period, and the latch stage is operable to latch the temporary interim output during the defined period using a common clock.

Abstract: Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage.

Abstract: A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.

Abstract: Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.

Abstract: Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sample an incoming signal. A reference signal, such as a Nyquist signal, is applied to a data input of each of the latches. Statistics of “early” and “late” corrections applied to at least one of the clocks by a bang-bang phase detector in the clock and data recovery system are evaluated and a delay of a clock buffer associated with the at least one clock is adjusted to obtain approximately a 50% early-to-late ratio for the at least one clock. The clock and data recovery system ensures that the early-to-late ratio for the sum of the plurality of clocks is approximately 50%.

Abstract: In order to reduce the area of a charge pump PLL, one may separate proportional component and integral component of the loop filter voltage, and add additional circuitry so as to make the integral component appear as though it is affected by a much larger value of capacitance than is actually used. In an aspect, a current mirror may be used to subtract a portion of the integral component of the loop filter voltage from the total loop filter voltage. The difference signal is then used to drive an oscillator in the charge pump PLL. In another aspect, a third integrator or auto-calibration loop is used to set a center frequency of the oscillator.

Abstract: A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal.