Abstract: A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal.

Abstract: Circuitry compensates for adverse effects resulting from leakage currents in loop filter capacitors for signal synthesizers, like PLLs. In one technique, leakage current in the loop filter's damping capacitor is compensated by driving the voltage across a matching capacitor and generating current for the damping capacitor based on current applied to the matching capacitor. In another technique, leakage current in the loop filter's transconductor capacitor is compensated by digitally accumulating differences between the damping capacitor voltage and a reference voltage, and then converting the accumulated difference into a (voltage or current) signal applied to the transconductor capacitor. In addition, the loop filter could have an analog transconductor path that generates a signal that is also applied to the transconductance capacitor.

Abstract: An electronic device, a method of manufacturing an electronic device and an integrated circuit that employs at least one such electronic device to couple first and second circuits together in an isolated fashion. In one embodiment, the electronic device includes a first conductive channel, a second conductive channel and an isolation layer. The isolation layer is formed from and over the first conductive channel, interposing the first conductive channel and the second conductive channel and configured both to isolate the second conductive channel electrically from the first conductive channel and transfer momentum between charge carriers in the first conductive channel and charge carriers in the second conductive channel.

Abstract: A phase-locked loop (PLL) having a digitally controlled oscillator (DCO), where the DCO receives a digital control signal generated by the PLL and an externally generated oscillator clock signal and generates an output signal having a frequency greater than that of the oscillator clock signal. In one embodiment, the DCO is an analog PLL, such as a fractional-N frequency synthesizer, that receives a two-part digital control signal corresponding to the integer and fractional portions of a desired multiplier. The feedback path within the DCO has a dual-modulus divider that is controlled by a modulus controller to apply, over time, an effective divisor value that achieves the desired degree of multiplication. PLLs of the present invention are especially applicable to low-bandwidth, low-noise applications, such as high-multiplication frequency synthesizers and clock filtering, that are integrated into digital ASICs.

Abstract: A circuit, such as a phase-lock loop (PLL), has an oscillator having a plurality of operating curves. During circuit auto-trim operations, the oscillator is automatically trimmed to an appropriate oscillator operating curve for use during normal circuit operations. In particular PLL embodiments, the PLL is a charge-pump PLL having a phase/frequency detector (PFD) that generates error signals based on comparing an input signal and a PLL feedback signal; a charge pump that generates amounts of charge corresponding to the error signals; a loop filter that accumulates the amounts of charge to generate a loop-filter voltage; and a voltage-controlled oscillator (VCO), where the VCO output signal is used to generate the PLL feedback signal. During normal PLL operations, the loop-filter voltage is applied to the voltage input of the VCO.

Abstract: A phase-locked loop (PLL) has a master circuit configured to a slave circuit. The slave circuit has a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator configured to operate as a closed-loop PLL. The master circuit has a phase detector and a charge pump that are similar to the corresponding components in the slave circuit. The master circuit is configured to receive two input signals with zero phase offset. As such, any net current charge generated by the master charge pump will be indicative of mismatch within the master phase detector and charge pump, and therefore, by analogy, indicative of mismatch within the slave phase detector and charge pump, as well. A voltage signal generated by the master circuit is applied to control the generation of currents by the slave charge pump in such a way as to compensate for static phase offset that would otherwise exist in the slave circuit.

Abstract: A phase-locked loop (PLL) has a phase detector (PD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The PD generates DOWN pulses based on differences in phase between an input signal and a feedback signal. The charge pump has an UP current source that generates a DC UP current and a DOWN current source that generates a DOWN current based on the DOWN pulses received from the phase detector. The charge pump generates a charge-pump current based on the DC UP current and the DOWN current. The loop filter receives the charge-pump current and generates a loop-filter voltage based on a net accumulation of charge from the charge-pump current. The VCO receives the loop-filter voltage and generates an output signal whose frequency is based on the loop-filter voltage, wherein the feedback signal is generated from the output signal.

Abstract: A phase-lock loop (PLL) has an oscillator having a plurality of operating curves. During PLL auto-trim operations, the oscillator is automatically trimmed to an appropriate oscillator operating curve for use during normal PLL operations. In particular embodiments, the PLL is a charge-pump PLL having a phase/frequency detector (PFD) that generates error signals based on comparing an input signal and a PLL feedback signal; a charge pump that generates amounts of charge corresponding to the error signals; a loop filter that accumulates the amounts of charge to generate a loop-filter voltage; and a voltage-controlled oscillator (VCO), where the VCO output signal is used to generate the PLL feedback signal. During normal PLL operations, the loop-filter voltage is applied to the voltage input of the VCO.

Abstract: A variable-length data alignment apparatus receives header data and blocks from different sources, forms a header based on the received header data and outputs the header followed by blocks. The variable-length data alignment apparatus has a RAM for storing the header data, and a buffer for storing the blocks. A processor produces a plurality of commands and processes the header data from the RAM. The commands are prosecuted in a multiplexer and a bit stream coder to form a header and to append the blocks, stored in the buffer, after the header.

Abstract: A method and system for tufting fabrics are disclosed. In addition a number of alternative tufting heads are disclosed. The method and system take into account at least one of the following factors: the direction of traverse with respect to filaments, any change in direction of traverse, the yarn type and thickness, the orientation of the needle with respect to the filaments, the distorting effect the needle has on the filament grid network when it is inserted into the backing, and the backing. The position of the needle relative to the positions of the tufts in the pattern is adjusted in order to compensate for positional errors introduced by the factors mentioned. The tufting heads are also modified to make them suitable for automation.

Abstract: A versatile escape run-level coder for use in a digital video signal processing apparatus which produces a run-level data and an escape prefix code carrying escape code and escape code length data. A selection logic detects the level of the level data in the run-level data. When the level is detected as in a mid range, three selectors select short length data, data from the code extender 13 which inserts meaningless 8-bit code, and data from code concatenator 1, respectively. The selected data are concatenated in a second code concatenator for forming a tailor made code which is 36-bit long, but the effective data length is, for example, 20 bits. When the level is detected as in a range above or below the mid range, the three selectors select long length data, data from the line carrying ESC code and data from either one of the two level coders, respectively.

Abstract: A digital squelch circuit for detecting valid data signals in a burst mode communication system, such as a packet-based local area network. Transitions in the input signal to the squelch circuit start a counter which asserts at least one signal a predetermined time from the transition. The absence or presence of the signal when the next transition in the input signal occurs determines if the frequency of the input signal is less than or greater than a frequency related to the predetermined time interval. When a predetermined number of transitions meeting the desired frequency requirement are received, the input signal is judged valid.

Abstract: Processing apparatus for photographic film, particularly intraoral xray film, in which the various processing stations are positioned in a circle about a central rotatable column. The column has an external spiral groove in which rides a pin carried by, and extending into the bore of, a hub which fits around the column. Rotation of the column moves the hub up or down, depending upon the direction of rotation. The hub carries a plurality of arms equal in number to the number of stations, seven in the apparatus disclosed. Each arm has a magnet for attaching a novel film holder which is detachable at the unloading station. After loading a film holder with film to be processed, the holder is loaded into the machine through a spring-pressed loading door onto a loading platform which moves the film holder upwardly to engage it with one of the arms when the door is closed.

Abstract: In a film duplicator original and copy sheets are initially brought together in unaligned relationship and permitted to drop under the influence of gravity along a predetermined path past an exposure station and into an alignment box where the ends of the sheets strike the bottom of the box to align the sheets. The aligned sheets are then transported back to the exposure station to expose the copy sheet. The sheets are then separated and exited from the duplicator.

Abstract: A method of controlling an embroidery machine (3) using a stitch processor (1) by interpreting a low level language program containing stitch commands and varying the stitch commands to vary certain parameters of the design. The parameters which may be varied in any combination thereof include any of the following stitch density, stitch length, size of the design independent of the stitch density, stitch spacing as a function of stitch length, orientation of the design, mirror image of the design and removing irregularities in the design. The parameters to be varied are entered by a keyboard/display (2). The program may be read from a paper tape reader (4), directly from a computer system (5) used to generate the original stitch commands or any other input device. The modified stitch commands may be fed directly to an embroidery machine or stored in any of the usual methods for communicating to an embroidery machine at a later date.

Abstract: A novel fully differential analog comparator having cascaded gain stages powered by two buses. The two buses are powered by a current source and a variable gain current mirror responsive to the current source. The current source and the current mirror isolate the buses from external power and ground to achieve high power supply noise immunity. True and complementary outputs of the comparator are provided having an adjustable output common mode voltage to optimize the driving of subsequent logic gates responsive to the comparator.

Abstract: A container for storing and transporting video cassettes of different sizes includes an array of flexible retaining posts affixed to one of the inner surfaces of the container and disposed in spaced relationship so to engage a single access opening in a video cassette in an interference fit manner, thus holding the cassette securely inside the container.