Patents by Inventor William C. Plants
William C. Plants has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100014357Abstract: A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.Type: ApplicationFiled: September 29, 2009Publication date: January 21, 2010Inventors: Joel Landry, William C. Plants, Randall Sexton
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Publication number: 20090292937Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.Type: ApplicationFiled: August 5, 2009Publication date: November 26, 2009Inventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kolkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William C. Plants
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Patent number: 7613943Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.Type: GrantFiled: October 31, 2007Date of Patent: November 3, 2009Assignee: Actel CorporationInventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kolkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William C. Plants
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Publication number: 20090212343Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: ApplicationFiled: April 2, 2009Publication date: August 27, 2009Applicant: ACTEL CORPORATIONInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Patent number: 7579869Abstract: A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming the programmable element; wherein at least one of the routing tracks is segmented into non-uniform lengths by the programmable element and the second routing track crosses-over to the first track position in a region adjacent to an edge of the repeatable block; and wherein a first plurality of the routing track sets proceed in a horizontal direction and a second plurality of the routing track sets proceed in a vertical direction.Type: GrantFiled: June 2, 2008Date of Patent: August 25, 2009Assignee: Actel CorporationInventors: Arunangshu Kundu, Eric Sather, William C. Plants
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Patent number: 7573093Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: October 29, 2007Date of Patent: August 11, 2009Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Patent number: 7558112Abstract: First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.Type: GrantFiled: July 15, 2008Date of Patent: July 7, 2009Assignee: Actel CorporationInventor: William C. Plants
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Patent number: 7543216Abstract: A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises providing serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals generated by row column counters, loading data from the serial data stream into the user assignable SRAM in response to address signals generated by row and column counters, loading a seed and signature from the serial data stream into a cyclic redundancy checking circuit, cycling data out of configuration SRAM and user assignable SRAM by the row and column counters, performing error checking on the data that has been cycled out of the configuration SRAM and out of the user assignable SRAM by the cyclic redundancy checking circuit, and generating an error signal when an error is detected by the error checking circuit.Type: GrantFiled: October 17, 2006Date of Patent: June 2, 2009Assignee: Actel CorporationInventor: William C. Plants
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Patent number: 7538382Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: October 29, 2007Date of Patent: May 26, 2009Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Patent number: 7538379Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: December 16, 2005Date of Patent: May 26, 2009Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Publication number: 20090106531Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.Type: ApplicationFiled: December 29, 2008Publication date: April 23, 2009Applicant: Actel CorporationInventors: Arunangshu Kundu, Arnold Goldfein, William C. Plants, David Hightower
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Publication number: 20090094475Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.Type: ApplicationFiled: December 17, 2008Publication date: April 9, 2009Applicant: ACTEL CORPORATIONInventors: William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James Joseph, Wayne W. Wong
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Patent number: 7516303Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.Type: GrantFiled: July 22, 2005Date of Patent: April 7, 2009Assignee: Actel CorporationInventors: Arunangshu Kundu, Arnold Goldfein, William C. Plants, David Hightower
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Patent number: 7487376Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.Type: GrantFiled: October 31, 2007Date of Patent: February 3, 2009Assignee: Actel CorporationInventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kolkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William C. Plants
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Patent number: 7484113Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.Type: GrantFiled: November 20, 2006Date of Patent: January 27, 2009Assignee: Actel CorporationInventors: William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James Joseph, Wayne W. Wong
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Patent number: 7473960Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.Type: GrantFiled: October 29, 2007Date of Patent: January 6, 2009Assignee: Actel CorporationInventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
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Publication number: 20080298116Abstract: A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.Type: ApplicationFiled: July 14, 2008Publication date: December 4, 2008Applicant: ACTEL CORPORATIONInventor: William C. Plants
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Publication number: 20080297191Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).Type: ApplicationFiled: July 23, 2008Publication date: December 4, 2008Applicant: ACTEL CORPORATIONInventor: William C. Plants
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Publication number: 20080276030Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks without being further connected to the SRAM bussing architecture.Type: ApplicationFiled: July 23, 2008Publication date: November 6, 2008Applicant: ACTEL CORPORATIONInventor: William C. Plants
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Publication number: 20080266955Abstract: First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.Type: ApplicationFiled: July 15, 2008Publication date: October 30, 2008Applicant: ACTEL CORPORATIONInventor: William C. Plants