Abstract: Systems and methods are disclosed for tracking an item using a RFID surveillance system. In some embodiments, a security controller is connected to a point of sale system with at least one RFID tag reader. In these embodiments, the RFID tag reader is associated with an area that is observable through a video camera. If the tag reader does not recognize information obtained from a RFID tag, the tag reader may activate the video camera. When the video camera is activated, the video camera may capture images and send them to a recording device.

Abstract: Systems and methods are disclosed for tracking an item using a RFID surveillance system. In some embodiments, a security controller is connected to a point of sale system with at least one RFID tag reader. In these embodiments, the RFID tag reader is associated with an area that is observable through a video camera. If the tag reader does not recognize information obtained from a RFID tag, the tag reader may activate the video camera. When the video camera is activated, the video camera may capture images and send them to a recording device.

Abstract: A surveillance and security system includes a plurality of detectors and cameras each associated with a zone of interest. Upon detection or sensing of an event within the zone, an event detection signal is generated and transmitted to a security system controller. The controller generates and transmits a notification message over a data network to a remote communications device notifying a user that an event has been detected by the surveillance and security system, and establishes a communication session. This enables a user of the remote communication device to remotely control the surveillance and security system, and activate or perform certain actions within the system.

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known.

Abstract: Fuse circuitry is presented which emulates fuse blowing in a temporary manner. As an embodiment, redundant elements of an integrated circuit may be enabled and/or tested prior to laser repair through the use of non-destructive fuse circuitry which emulates fuse blowing. An integrated circuit has a plurality of addressable elements and a plurality of redundant elements, which may be used to replace defective addressable elements. Each redundant element has a non-destructive fuse circuit associated with it which may be used to enable and/or test the redundant element prior to laser repair by emulating the blowing of a fuse contained in the non-destructive fuse circuit. The non-destructive fuse circuit is comprised of a fuse connected to a control logic element, such as an inverter, wherein the control logic element is in turn controlled by a test signal. Emulation of blowing the fuse or not blowing the fuse is accomplished by the logic level of the test signal.

Abstract: A clock generator circuit for producing a clock signal while drawing reduced current drain is disclosed. The clock generator circuit includes a crystal oscillator which produces a periodic signal having a relatively small voltage swing, controlled by one or more reference voltages; the reference voltages are preferably produced by a sub-threshold biased voltage reference circuit. The small signal output of the crystal oscillator is applied to the first of a series of frequency divider stages, prior to amplification by a level shift circuit. Each divider stage includes a current switch which switches the current drawn through current divider legs to produce output signals to latches in the divider stage. Each divider stage also includes one or more current source switched latches, each controlled by current sources that are switched by the current switch.

Abstract: According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. The structure is a high impedance device which is placed on the end of select lines so that if a select line is broken during fabrication, the high impedance device will hold the broken end of the select line to the desired deselect voltage. Select lines which have a driver at one end only and are broken during fabrication, but have the high impedance device on the other end, are not allowed to float. The high impedance device is also suitable for select lines which are not broken and previously were anchored at just one end. Suitable high impedance devices include a reverse biased diode, a weak transistor, a poly R memory cell load device, and an ON or OFF TFT memory cell load device.

Abstract: A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor.

Abstract: A semiconductor memory including test circuitry for directly determining the functionality of internal circuitry. The gates of test transistors are connected to the ends of signal lines in the memory, examples of which include bit lines, row or word lines, and control signal lines. Upon entry into a special test mode, the test transistors are biased to a voltage such that the active signal, if present, will turn on the test transistor and produce a signal indicating whether or not the active signal reached the test transistor. Multiple test transistors may be used to provide additional information, including the presence of short circuits, and the operation of multiple circuits within the memory.

Abstract: Circuits and methods for generating a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device is disclosed. In a first embodiment, a delay circuit is provided for generating an output clock signal for controlling a circuit internal to an integrated circuit, such as a clocked sense amplifier in a memory device, relative to an earlier timing signal, such as a row select signal. The delay circuit is implemented by components having their design parameters, such as transistor dimensions and transistor orientation, corresponding to elements in an active portion of the circuit, such as memory cell transistors.

Abstract: A push-pull output driver including two transistors in series, one transistor having its body bias controlled by logic circuitry commanded by the driver input. The driver has a pair of transistors in series, the transistor inputs being complementary to create a push-pull amplifier. A switching transistor is controlled by the inverse of the driver input signal and acts as a switch at the pull-up transistor well-tie. When the driver input is high, the switching transistor is off allowing the well-tie to the pull-up transistor to be connected to the driver output. When the input is low, the switching transistor turns on, switching the well-tie of the pull-up transistor to ground. By controlling the body bias of the pull-up transistor in this way, the switching speed of the output driver is significantly increased. When the output driver is in a disabled tri-state mode, the series transistors, and the switching transistor, are turned off.

Abstract: An integrated circuit having a memory, and a method of operating the same, which provides for improved test efficiency. The memory includes static random access memory cells which power up in a preferred state; the preferred state draws less standby power, and is less susceptible to noise and other undesired effects which could cause upset of the stored data state. The method of testing the memory includes writing the memory cells with the complement of the preferred data state, so that all memory cells contain the higher current state; measurement of the standby current after the writing of the complement of the preferred data state will thus measure the worst case standby current. The method of testing may also include a disturb test, where the cell under test, or a neighboring cell in an adjacent row, is repeatedly accessed; such disturbing thus performs the worst case test, since the preferred state is more stable than its complement.

Abstract: A voltage level sense circuit that has temperature compensation is disclosed. The circuit includes charge-sharing capacitors in each of an input leg and a reference leg. The charge-sharing capacitors are precharged to voltages that are integral multiples of the forward bias voltage drop across the base-emitter junction of a bipolar transistor. The bipolar transistors in the input leg differ from those in the reference leg, so that the difference in base-emitter on voltages increases with temperature. The increasing difference in base-emitter on voltage compensates for the decrease in the absolute value of the base-emitter on voltage with temperature. Voltage level sensing is accomplished by sampling the input voltage with a capacitor, charge-sharing the sampled voltage with one of the precharged charge-sharing capacitors, and coupling the charge-shared result to an input of a differential amplifier comparator.

Abstract: According to the present invention, a first circuit is used to detect a positive voltage transition on a signal line. A second circuit is used to detect a negative voltage transition on the signal line. Upon detecting a transition, the first circuit will drive the signal line high. The second circuit pulls the line to ground after sensing a negative voltage transition. A delay circuit determines the time period in which the first or second circuit is connected to the signal line.

Abstract: A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.

Abstract: An integrated circuit having a memory, and a method of operating the same, which provides for improved test efficiency. The memory includes static random access memory cells which power up in a preferred state; the preferred state draws less standby power, and is less susceptible to noise and other undesired effects which could cause upset of the stored data state. The method of testing the memory includes writing the memory cells with the complement of the preferred data state, so that all memory cells contain the higher current state; measurement of the standby current after the writing of the complement of the preferred data state will thus measure the worst case standby current. The method of testing may also include a disturb test, where the cell under test, or a neighboring cell in an adjacent row, is repeatedly accessed; such disturbing thus performs the worst case test, since the preferred state is more stable than its complement.

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known.

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known.

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known.

Abstract: According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. The structure is a high impedance device which is placed on the end of select lines so that if a select line is broken during fabrication, the high impedance device, will hold the broken end of the select line to the desired deselect voltage. Select lines which have a driver at one end only and are broken during fabrication, but have the high impedance device on the other end, are not allowed to float. The high impedance device is also suitable for select lines which are not broken and previously were anchored at just one end. Suitable high impedance devices include a reverse biased diode, a weak transistor, a poly R memory cell load device, and an ON or OFF TFT memory cell load device.