Structure for deselective broken select lines in memory arrays
According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. The structure is a high impedance device which is placed on the end of select lines so that if a select line is broken during fabrication, the high impedance device, will hold the broken end of the select line to the desired deselect voltage. Select lines which have a driver at one end only and are broken during fabrication, but have the high impedance device on the other end, are not allowed to float. The high impedance device is also suitable for select lines which are not broken and previously were anchored at just one end. Suitable high impedance devices include a reverse biased diode, a weak transistor, a poly R memory cell load device, and an ON or OFF TFT memory cell load device.
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Claims
1. Memory array circuitry for selecting a portion of a memory array, comprising:
- a plurality of memory cells;
- a plurality of select lines which select a portion of the memory cells in the memory array when set to a select voltage level and which deselect a portion of the memory array when set to a deselect voltage level, each select line having a first end and a second end, with the first end of a select line connected to a driver; and
- a plurality of high impedance reverse biased diodes, with a reverse biased diode connected to the second end of the select line which holds the select line to the deselect voltage level if the select line is broken.
2. The circuitry of claim 1, wherein the select line is a master row line.
3. The circuitry of claim 1, wherein the select line is a word line.
4. The circuitry of claim 1, wherein the high impedance reverse biased diode leaks charge, thereby pulling the select line, to which it is connected, to the deselect voltage level.
6. The circuitry of claim 5, wherein the word lines are connected to the master row lines through at least one of a row decode logic and driver circuitry.
7. The circuitry of claim 6, wherein the master row lines are connected to at least one of a master row decode logic lock which provides the driver on the first end of each of the master row lines.
8. The circuitry of claim 6, wherein the driver on the first end of each of the word lines is provided by the row decode logic and driver circuitry to which it is connected.
9. The circuitry of claim 5, wherein the high impedance reverse biased diode leaks charge, thereby pulling the select line, to which it is connected, to the deselect voltage level..Iadd.
10. Memory array circuitry for selecting a portion of a memory array, comprising:
- a plurality of memory cells;
- a plurality of select lines which select a portion of the memory cells in the memory array when set to a select state and which deselect a portion of the memory array when set to a deselect state, each select line having a first end and a second end, with the first end of a select line connected to a driver; and
- a plurality of high impedance reverse biased diodes, with a reverse biased diode connected to the second end of the select line which holds the second end of the select line to the deselect state if the select line is broken..Iaddend..Iadd.11. The circuitry of claim 10, wherein the select line is a master row line..Iaddend..Iadd.12. The circuitry of claim 10, wherein the select line is a word line..Iaddend..Iadd.13. The circuitry of claim 10, wherein the high impedance reverse biased diode leaks charge, thereby pulling the select line, to which it is connected, to a deselect
voltage..Iaddend..Iadd.14. Memory array circuitry for selecting a portion of a memory array, comprising:
- a plurality of local row decoders connected to a plurality of memory cells;
- a plurality of select lines, both master row lines and word lines, connected to the local row decoders which select a portion of the memory array when set to a select state and which deselect a portion of the memory array when set to a deselect state, each select line having a first end and a second end, with the first end of a select line connected to a driver; and
- a plurality of high impedance reverse biased diodes, with a reverse biased diode connected to the second end of the select line which holds the second end of the select line to the deselect state if the select line is broken..Iaddend..Iadd.15. The circuitry of claim 14, wherein the word lines are connected to the master row lines through at least one of a row decode logic and driver circuitry..Iaddend..Iadd.16. The circuitry of claim 15, wherein the master row lines are connected to at least one of a master row decode logic block which provides the driver on the first end of each of the master row lines..Iaddend..Iadd.17. The circuitry of claim 15, wherein the driver on the first end of each of the word lines is provided by the row decode logic and driver circuitry to which it is connected..Iaddend..Iadd.18. The circuitry of claim 14, wherein the high impedance reverse biased diode leaks charge, thereby pulling the select line, to which it is connected, to a deselect voltage level..Iaddend.
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Type: Grant
Filed: Nov 7, 1997
Date of Patent: Sep 28, 1999
Assignee: STMicroelectronics, Inc. (Carrollton, TX)
Inventor: William C. Slemmer (Dallas, TX)
Primary Examiner: Son T. Dinh
Law Firm: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
Application Number: 8/966,042
International Classification: G11C 700;
