Patents by Inventor William Cote

William Cote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240091708
    Abstract: Wastewater is treated though primary treatment of the water by way of a micro-sieve to produce a primary effluent and primary sludge. There is secondary treatment of the primary effluent by way of a membrane bioreactor (MBR) or an integrated fixed film activated sludge (IFAS) reactor to produce a secondary effluent and a waste activated sludge. The micro-sieve may have openings of 250 microns or less, for example about 150 microns. In a process, a gas transfer membrane is immersed in water. Pressurized air flows into the gas transfer membrane. An exhaust gas is withdrawn from the gas transfer membrane and used to produce bubbles from an aerator immersed in the water.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 21, 2024
    Inventors: Pierre Lucien COTE, Steven Kristian PEDERSEN, Wajahat Hussain SYED, Jeffrey Gerard PEETERS, Nicholas William H. ADAMS, Youngseck HONG, Geert-Henk KOOPS, James John ROYSTON
  • Patent number: 11588958
    Abstract: A probe assembly for a process vessel for viewing the inside of the vessel, the probe assembly includes an elongated bracket, an elongated frame, an ICPC unit, and a camera unit. The elongated bracket has a front face and a rear face, the elongated bracket having an upper portion and a lower portion, the lower portion has a first aperture. The elongated frame has a proximal end and a distal end, the distal end of the elongated frame is coupled to the upper portion of the front face of the bracket. The ICPC unit includes a housing that has a front wall, a rear wall, and side wall extended between the front wall and the rear wall, the front wall has a second aperture, the rear wall has a third aperture.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: February 21, 2023
    Inventors: Chen Chen, William Cote, Paul Ream
  • Publication number: 20220116515
    Abstract: A probe assembly for a process vessel for viewing the inside of the vessel, the probe assembly includes an elongated bracket, an elongated frame, an ICPC unit, and a camera unit. The elongated bracket has a front face and a rear face, the elongated bracket having an upper portion and a lower portion, the lower portion has a first aperture. The elongated frame has a proximal end and a distal end, the distal end of the elongated frame is coupled to the upper portion of the front face of the bracket. The ICPC unit includes a housing that has a front wall, a rear wall, and side wall extended between the front wall and the rear wall, the front wall has a second aperture, the rear wall has a third aperture.
    Type: Application
    Filed: October 4, 2021
    Publication date: April 14, 2022
    Inventors: Chen Chen, William Cote, Paul Ream
  • Patent number: 8928057
    Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: William Cote, Johnathan E. Faltermeier, Babar A. Khan, Ravikumar Ramachandran, Theodorus E. Standaert, Xinhui Wang
  • Patent number: 8748252
    Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, William Cote, Laertis Economikos, Young-Hee Kim, Dae-Gyu Park, Theodorus Eduardus Standaert, Kenneth Jay Stein, YS Suh, Min Yang
  • Publication number: 20140151772
    Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Cote, Johnathan E. Faltermeier, Babar A. Khan, Ravikumar Ramachandran, Theodorus E. Standaert, Xinhui Wang
  • Publication number: 20140148003
    Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, William Cote, Laertis Economikos, Young-Hee Kim, Dae-Gyu Park, Theodorus Eduardus Standaert, Kenneth Jay Stein, YS Suh, Min Yang
  • Patent number: 8340800
    Abstract: Monitoring a process sector in a production facility includes establishing a tool defect index associated with a process sector in the production facility. The tool defect index includes a signal representing a defect factor associated with a tool in the process sector. Monitoring the process also requires determining whether the defect factor is a known defect factor or an unknown defect factor, and analyzing a unit from the tool if the defect factor is an unknown defect factor. Monitoring the process further requires identifying at least one defect on the unit from the tool, establishing that the at least one defect is a significant defect, determining cause of the significant defect, and creating an alert indicating that the tool associated with the process sector is producing units having significant defects.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: William Cote, Michael P. Guse, Mark E. Lagus, James Rice, Yunsheng Song
  • Patent number: 8293634
    Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Felix P. Anderson, William Cote, Daniel C. Edelstein, Thomas L. McDevitt, Anthony K. Stamper
  • Patent number: 8288281
    Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
  • Patent number: 8242544
    Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
  • Publication number: 20120129336
    Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.
    Type: Application
    Filed: January 27, 2012
    Publication date: May 24, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Felix P. ANDERSON, William COTE, Daniel C. EDELSTEIN, Thomas L. MCDEVITT, Anthony K. STAMPER
  • Patent number: 8032626
    Abstract: A service monitor and a browser monitor determine performance metrics on both a server and a client in connection with a distributed application running on a network. While applicable to other types of distributed application data, an example is described in which a Web page is requested by a user running a browser program on the client computer. In response, the server transmits the requested Web page, along with JavaScript code that defines a browser monitor, to the client. A browser monitoring function controlled by this code determines a plurality of different performance metrics related to the access of Web pages by the client. In addition, the server monitor determines performance metrics specific to its function in providing the Web page to the client. A correlated performance metric is determined by combining a server performance metric with a browser performance metric.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: October 4, 2011
    Assignee: Symantec Corporation
    Inventors: Ethan George Russell, Stephen William Cote, Erkki Ville Juhani Aikas, Brian David Marsh, John Bradley Chen
  • Publication number: 20100279508
    Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.
    Type: Application
    Filed: July 16, 2010
    Publication date: November 4, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
  • Patent number: 7803708
    Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: September 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Xiaomeng Chen, William Cote, Anthony K Stamper, Arthur C Winslow
  • Publication number: 20100032829
    Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.
    Type: Application
    Filed: August 7, 2008
    Publication date: February 11, 2010
    Inventors: Felix P. Anderson, William Cote, Daniel C. Edelstein, Thomas L. McDevitt, Anthony K. Stamper
  • Publication number: 20100017010
    Abstract: Monitoring a process sector in a production facility includes establishing a tool defect index associated with a process sector in the production facility. The tool defect index includes a signal representing a defect factor associated with a tool in the process sector. Monitoring the process also requires determining whether the defect factor is a known defect factor or an unknown defect factor, and analyzing a unit from the tool if the defect factor is an unknown defect factor. Monitoring the process further requires identifying at least one defect on the unit from the tool, establishing that the at least one defect is a significant defect, determining cause of the significant defect, and creating an alert indicating that the tool associated with the process sector is producing units having significant defects.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 21, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Cote, Michael Guse, Mark E. Lagus, James Rice, Yunsheng Song
  • Patent number: 7600014
    Abstract: A service monitor and a browser monitor determine performance metrics on both a server and a client in connection with a distributed application running on a network. While applicable to other types of distributed application data, an example is described in which a Web page is requested by a user running a browser program on the client computer. In response, the server transmits the requested Web page, along with JavaScript code that defines a browser monitor, to the client. A browser monitoring function controlled by this code determines a plurality of different performance metrics related to the access of Web pages by the client. In addition, the server monitor determines performance metrics specific to its function in providing the Web page to the client. A correlated performance metric is determined by combining a server performance metric with a browser performance metric.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: October 6, 2009
    Assignee: Symantec Corporation
    Inventors: Ethan George Russell, Stephen William Cote, Erkki Ville Juhani Aikas, Brian David Marsh, John Bradley Chen
  • Publication number: 20070221990
    Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 27, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Cote, Oliver Patterson
  • Publication number: 20070204447
    Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
    Type: Application
    Filed: February 16, 2007
    Publication date: September 6, 2007
    Applicant: International Business Machines Corporation
    Inventors: Kerry Bernstein, John Bracchitta, William Cote, Tak Ning, Wilbur Pricer