Patents by Inventor William D. Cox

William D. Cox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190341033
    Abstract: Systems and methods for handling responses from voice services. In some embodiments, an Information Handling System (IHS) may include: a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: transmit an audio instruction to a voice services engine, receive a response to the audio instruction, and output a notification associated with the response using an output setting selected based upon a context of the IHS.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Applicant: Dell Products, L.P.
    Inventors: Marc Randall Hammons, Todd Erick Swierk, Tyler Ryan Cox, William D.T. Nix
  • Patent number: 7972907
    Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: July 5, 2011
    Assignees: Triad Semiconductor, Inc., ViAsic, Inc.
    Inventors: James C. Kemerling, David Ihme, William D. Cox
  • Patent number: 7930670
    Abstract: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: April 19, 2011
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Patent number: 7692309
    Abstract: An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and a second non-customized metal routing layer, is disposed on top of the plurality of non-customized layers. A second routing grid, which includes a third non-customized metal routing layer, another customized via layer, and a fourth non-customized metal routing layer, is disposed above the first routing grid. A non-customized via layer is disposed above the first routing grid and beneath the second routing grid. The routing grids and the non-customized via layer collectively facilitate routing connections to and from the logic cells.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: April 6, 2010
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Patent number: 7626272
    Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: December 1, 2009
    Assignees: Triad Semiconductor, Inc., ViAsic, Inc.
    Inventors: James C. Kemerling, David Ihme, William D. Cox
  • Patent number: 7595229
    Abstract: A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: September 29, 2009
    Assignees: Triad Semiconductor, Inc., Viasic, Inc.
    Inventors: David Ihme, James C. Kemerling, William D. Cox
  • Publication number: 20090210848
    Abstract: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
    Type: Application
    Filed: April 29, 2009
    Publication date: August 20, 2009
    Applicant: VIASIC, INC.
    Inventor: William D. COX
  • Patent number: 7538580
    Abstract: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: May 26, 2009
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Publication number: 20090065813
    Abstract: An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and a second non-customized metal routing layer, is disposed on top of the plurality of non-customized layers. A second routing grid, which includes a third non-customized metal routing layer, another customized via layer, and a fourth non-customized metal routing layer, is disposed above the first routing grid. A non-customized via layer is disposed above the first routing grid and beneath the second routing grid. The routing grids and the non-customized via layer collectively facilitate routing connections to and from the logic cells.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 12, 2009
    Applicant: VIASIC, INC.
    Inventor: William D. COX
  • Publication number: 20090061567
    Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.
    Type: Application
    Filed: November 11, 2008
    Publication date: March 5, 2009
    Applicants: Triad Semiconductor, Inc., ViAsic, Inc.
    Inventors: James C. Kemerling, David Ihme, William D. Cox
  • Publication number: 20090032968
    Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.
    Type: Application
    Filed: October 7, 2008
    Publication date: February 5, 2009
    Applicants: Triad Semiconductor, Inc., ViAsic, Inc.
    Inventors: James C. Kemerling, David Ihme, William D. Cox
  • Patent number: 7449371
    Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: November 11, 2008
    Assignees: Triad Semiconductor, Viasic, Inc.
    Inventors: James C. Kemerling, David Ihme, William D Cox
  • Patent number: 7378874
    Abstract: Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized and converted to parallel elements as a post-process. The drive characteristics of the logical gates are retained during the conversion to the physical gate equivalents in the standard cell architecture. The logic cells in the device may include, for example, at least two two-input multiplexers.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: May 27, 2008
    Assignee: ViASIC, Inc.
    Inventors: Bhaskar Bharath, William D. Cox
  • Publication number: 20080054939
    Abstract: Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized and converted to parallel elements as a post-process. The drive characteristics of the logical gates are retained during the conversion to the physical gate equivalents in the standard cell architecture. The logic cells in the device may include, for example, at least two two-input multiplexors.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Applicant: VIASIC, INC.
    Inventors: Bhaskar BHARATH, William D. COX
  • Patent number: 7335966
    Abstract: A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: February 26, 2008
    Assignees: Triad Semiconductor, Inc., ViASIC, Inc.
    Inventors: David Ihme, James C. Kemerling, William D. Cox
  • Patent number: 7334208
    Abstract: Customization of structured ASIC devices using pre-process extraction of routing information. Embodiments of the invention can enable a router that can automatically extract a routing graph for a structured ASIC, where the routing graph represents available routing resources on fixed metal layers. The routing graph can be extracted as a pre-process, and saved in a technology file for later use by the router. Additionally, each unique fixed metal wire type found in the layout can be characterized with a master wire definition, including resistance and capacitance estimates. In some embodiments, a global-routing graph can further be extracted from a detailed routing graph.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: February 19, 2008
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Patent number: 7248071
    Abstract: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: July 24, 2007
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Patent number: 6873185
    Abstract: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: March 29, 2005
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Patent number: 6693454
    Abstract: Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of configurable metal for routing. The extra semiconductor area in the cells of a metal limited device is used to implement general purpose RAM. Common select lines and read/write lines for the RAM are embedded in the base cells so that the configurable metal (whether via or actual metal layer) over the RAM can be used for routing logic.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: February 17, 2004
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Publication number: 20030234666
    Abstract: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
    Type: Application
    Filed: September 4, 2002
    Publication date: December 25, 2003
    Inventor: William D. Cox