Abstract: Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of configurable metal for routing. The extra semiconductor area in the cells of a metal limited device is used to implement general purpose RAM. Common select lines and read/write lines for the RAM are embedded in the base cells so that the configurable metal (whether via or actual metal layer) over the RAM can be used for routing logic.

Abstract: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.

Abstract: A semiconductor device and method of testing the device having a plurality of logic cells interconnected using vias to connect routing tracks that are disposed among a plurality of layers in the device. The logic cells in the device including at least two three-input look-up tables, one two-input look-up table and a flip-flop. The components in the logic cell are connected so that any look-up table can drive at least one input of any other look-up table and where the flip-flop is connected to the look-up tables so that any look-up table can drive an input of the flip-flop.

Abstract: Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of configurable metal for routing. The extra semiconductor area in the cells of a metal limited device is used to implement general purpose RAM. Common select lines and read/write lines for the RAM are embedded in the base cells so that the configurable metal (whether via or actual metal layer) over the RAM can be used for routing logic.

Abstract: A semiconductor device and method of testing the device having a plurality of logic cells interconnected using vias to connect routing tracks that are disposed among a plurality of layers in the device. The logic cells in the device including at least two three-input look-up tables, one two-input look-up table and a flip-flop. The components in the logic cell are connected so that any look-up table can drive at least one input of any other look-up table and where the flip-flop is connected to the look-up tables so that any look-up table can drive an input of the flip-flop.

Abstract: A semiconductor device and method of testing the device having a plurality of logic cells interconnected using vias to connect routing tracks that are disposed among a plurality of layers in the device. The logic cells in the device including at least two three-input look-up tables, one two-input look-up table and a flip-flop. The components in the logic cell are connected so that any look-up table can drive at least one input of any other look-up table and where the flip-flop is connected to the look-up tables so that any look-up table can drive an input of the flip-flop.

Abstract: An interface cell for a programmable integrated circuit includes a pad, an input buffer, a first routing conductor, a plurality of second routing conductors, and a plurality of antifuses. The input of the input buffer is coupled to the pad and the output of the input buffer is coupled to the first routing conductor so that an input signal from the pad can be supplied onto the first routing conductor without passing through any programmed antifuses. The second routing conductors extend parallel to one another in a direction perpendicular to the direction in which the first routing conductor extends. The second routing conductors cross the first routing conductor and then pass out of the interface cell and into a routing channel of the programmable integrated circuit. One of the antifuses is disposed at each location where one of the second routing conductors crosses the first routing conductor.

Abstract: Select sets of a logic function corresponding to an output of a first logic circuit are determined. These select sets are used to obtain a second logic circuit, the logic function corresponding to the output of which is the same as the logic function corresponding to the output of the first logic circuit. A propagation delay through the second logic circuit may be smaller than a corresponding delay through the first logic circuit. Sometimes, such a smaller propagation delay through the second logic circuit results in the second logic circuit having a smaller critical path delay. The second logic circuit may therefore have a greater maximum operating speed than the first logic circuit.

Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

Abstract: A sequence of antifuses to be programmed is determined by: determining whether a first antifuse of an unordered list of antifuses to be programmed could be programmed last without programming any antifuses which are not to be programmed, determining whether a second antifuse of the unordered list could be programmed last without programming any antifuses which are not be programmed, and determining whether the first and second antifuses could be programmed simultaneously without programming any antifuses which are not to be programmed. In this way, a programming set of antifuses which could be programmed simultaneously is determined. Once determined, the antifuses making up the programming set are added to the head of an ordered list and are removed from the unordered list. By repeatedly determining programming sets of antifuses and adding each successive set of antifuses to an ordered list of antifuses, an antifuse programming sequence is developed.

Abstract: A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current flowing through the second antifuse exceeds a maximum permissible operating current of the first antifuse but does not exceed a maximum permissible operating current of the second antifuse, whereby an actual operating current flowing through the first antifuse does not exceed the maximum permissible operating current of the first antifuse, and whereby an actual operating current flowing through the second antifuse does not exceed the maximum permissible operating current of the second antifuse. By allowing the use of a programming method on some antifuses which would not be adequate for the programming of other antifuses, the realization of user-specific circuits in field programmable devices is facilitated and the reliability of user-specific circuits realized in field programmable devices is enhanced.

Abstract: A logic circuit is implemented on a macrocell of a field programmable device using select sets of a logic function which represents a transformation of the one or more input signals of the logic circuit to the output signal of the logic circuit. Select sets of a logic function are determined (i) by grouping input signals which correspond to equal co-factors of the logic function or (ii) by grouping input signals such that one input signal of a group never appears in a term of the logic function in a greedy phase-minimized RMF canonical form without all other input signals of the group. The logic circuit is implemented on a macrocell which includes a circuit element which selects one of two or more input signals according to one or more select signals, each of which is driven by a respective logic gate. Examples of such circuit elements include multiplexers and random access memory (RAM).

Abstract: A method for reducing the resistance of a programing path through a programmable antifuse from a programming voltage to ground. A previously programmed helper antifuse connected somewhere along a two branch programming path is connected to either the programming voltage or to ground. As a result, a three branch programming path is established from the programming voltage to the antifuse to be programmed and from the antifuse to be programmed to ground. By adding the third branch to the programming path, the resistance of the programming path is reduced, thereby allowing a higher voltage to be dropped across the antifuse to be programmed during programming and thereby allowing increased current flow through the antifuse to be programmed during programming. In another embodiment, two or more helper antifuses are used to establish a four or more branch programming path having a still lower resistance from the programming voltage to ground.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

Abstract: A method for reducing the resistance of a programming path through a programmable antifuse from a programming voltage to ground. A previously programmed helper antifuse connected somewhere along a two branch programming path is connected to either the programming voltage or to ground. As a result, a three branch programming path is established from the programming voltage to the antifuse to be programmed and from the antifuse to be programmed to ground. By adding the third branch to the programming path, the resistance of the programming path is reduced, thereby allowing a higher voltage to be dropped across the antifuse to be programmed during programming and thereby allowing increased current flow through the antifuse to be programmed during programming. In another embodiment, two or more helper antifuses are used to establish a four or more branch programming path having a still lower resistance from the programming voltage to ground.