Patents by Inventor William Dally
William Dally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9069684Abstract: A system, method, and computer program product are provided for invalidating cache lines. In use, one or more cache lines that hold data from within a region of a memory address space are invalidated.Type: GrantFiled: July 16, 2012Date of Patent: June 30, 2015Assignee: NVIDIA CorporationInventor: William Dally
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Patent number: 8742796Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.Type: GrantFiled: January 18, 2011Date of Patent: June 3, 2014Assignee: Nvidia CorporationInventors: William Dally, Jonah Alben
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Publication number: 20140019691Abstract: A system, method, and computer program product are provided for invalidating cache lines. In use, one or more cache lines that hold data from within a region of a memory address space are invalidated.Type: ApplicationFiled: July 16, 2012Publication date: January 16, 2014Applicant: NVIDIA CORPORATIONInventor: William Dally
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Patent number: 8428207Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.Type: GrantFiled: November 30, 2010Date of Patent: April 23, 2013Assignee: NVIDIA CorporationInventors: William Dally, Stephen G. Tell
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Publication number: 20120182056Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.Type: ApplicationFiled: January 18, 2011Publication date: July 19, 2012Applicant: NVIDIA CORPORATIONInventors: William Dally, Jonah Alben
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Publication number: 20070263757Abstract: A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.Type: ApplicationFiled: July 18, 2007Publication date: November 15, 2007Inventors: William Dally, John Edmondson, Ramin Farjad-Rad
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Publication number: 20070241821Abstract: An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval.Type: ApplicationFiled: April 18, 2006Publication date: October 18, 2007Inventors: William Dally, John Poulton
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Publication number: 20070239967Abstract: A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seamless transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low overhead interrupts.Type: ApplicationFiled: March 27, 2007Publication date: October 11, 2007Applicant: MIPS Technologies, Inc.Inventors: William Dally, W. Hays, Robert Gelinas, Sol Katzman, Sam Rosen, Staffan Ericsson
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Publication number: 20070150700Abstract: A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed are divided into two groups based on whether or not they satisfy a given condition by e.g., steering each to one of the two index vectors. Once the data have been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication. Other examples of conditional operations include combining one or more input vectors into a single output vector based on a condition vector, conditional vector switching, conditional vector combining, and conditional vector load balancing.Type: ApplicationFiled: August 28, 2006Publication date: June 28, 2007Applicants: The Board of Trustees of the Leland Stanford Junior University, The Massachusetts Institute of TechnologyInventors: William Dally, Scott Rixner, John Owens, Ujval Kapasi
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Publication number: 20070140240Abstract: An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links.Type: ApplicationFiled: February 9, 2007Publication date: June 21, 2007Inventors: William Dally, Philip Carvey, Larry Dennison, P. King
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Publication number: 20070106886Abstract: Systems and methods that allow for performing a single transaction that both commands a device to perform an action and return the result to a processor without the processor having to send a separate request for the result. In addition, a processor may perform a context switch switching between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing.Type: ApplicationFiled: October 25, 2006Publication date: May 10, 2007Applicant: MIPS Technologies, Inc.Inventors: Robert Gelinas, W. Hays, Sol Katzman, William Dally
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Publication number: 20070041468Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.Type: ApplicationFiled: August 31, 2006Publication date: February 22, 2007Applicant: Massachusetts Institute of TechnologyInventor: William Dally
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Publication number: 20070041469Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.Type: ApplicationFiled: August 31, 2006Publication date: February 22, 2007Inventor: William Dally
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Publication number: 20070038626Abstract: Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.Type: ApplicationFiled: October 18, 2006Publication date: February 15, 2007Inventors: Gregory Waters, Larry Dennison, Philip Carvey, William Dally, William Mann
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Publication number: 20070002966Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.Type: ApplicationFiled: August 31, 2006Publication date: January 4, 2007Inventor: William Dally
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Publication number: 20070002967Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.Type: ApplicationFiled: August 31, 2006Publication date: January 4, 2007Applicant: Massachusetts Institute of TechnologyInventor: William Dally
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Publication number: 20060291585Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.Type: ApplicationFiled: August 31, 2006Publication date: December 28, 2006Applicant: Massachusetts Institute of TechnologyInventor: William Dally
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Publication number: 20060291586Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.Type: ApplicationFiled: August 31, 2006Publication date: December 28, 2006Applicant: Massachusetts Institute of TechnologyInventor: William Dally
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Publication number: 20060291587Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.Type: ApplicationFiled: August 31, 2006Publication date: December 28, 2006Applicant: Massachusetts Institute of TechnologyInventor: William Dally
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Publication number: 20060280260Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.Type: ApplicationFiled: July 10, 2006Publication date: December 14, 2006Inventor: William Dally