Digital transmitter
An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.
This application is a continuation of application Ser. No. 10/372,630, filed on Feb. 24, 2003 which is a continuation of application Ser. No. 09/852,481, filed on May 10, 2001, now U.S. Pat. No. 6,542,555, which is a continuation of Ser. No. 08/882,252, filed on Jun. 25, 1997, now U.S. Pat. No. 6,266,379, which is a continuation-in-part of Ser. No. 08/880,980, filed on Jun. 23, 1997, which claims the benefit of U.S. Provisional Application No. 60/050,098, filed on Jun. 20, 1997. The entire teachings of the above applications are incorporated herein by reference.
GOVERNMENT SUPPORTThe invention was supported, in whole or in part, by a grant No. F19628-92-C-0045 from Department of the Air Force. The Government has certain rights in the invention.
BACKGROUND OF THE INVENTIONThe performance of many digital systems is limited by the interconnection bandwidth between chips, boards, and cabinets. As VLSI technology continues to scale, system bandwidth will become an even more significant bottleneck as the number of I/Os scales more slowly than the bandwidth demands of on-chip logic. Also, off-chip signaling rates have historically scaled more slowly than on-chip clock rates. Most digital systems today use full-swing unterminated signaling methods that are unsuited for data rates over 100 MHz on one meter wires. Even good current-mode signaling methods with matched terminations and carefully controlled line and connector impedance are limited to about 1 GHz by the frequency-dependent attenuation of copper lines. Without new approaches to high-speed signaling, bandwidth will stop scaling with technology when we reach these limits.
SUMMARY OF THE INVENTIONConventional approaches to dealing with frequency dependent attenuation on transmission lines have been based on equalization, either in the transmitter or the receiver. For example, Tomlinson precoding is used in modems, and digital equalization in binary communication channels has been suggested in U.S. Pat. No. 4,374,426 to Burlage et al. However, such systems cannot scale to very high data rate binary or multilevel systems having bandwidths extending from near DC to greater than 100 MHz. Above 100 MHz, there is substantial attenuation due to skin effect resistance on conventional transmission lines.
The present invention enables equalizers which can be implemented as digital filters operating at acceptable clock speeds. For example, a three gigabit per second (Gbps) system can be implemented using 400 Mbps circuitry. The invention has particular application to nonmodulated, high data-rate, binary or multilevel systems as found locally within a data processor cabinet or on a local area network.
In accordance with the present invention, a digital transmitter comprises an equalizer which emphasizes transition signal levels relative to repeated signal levels. In particular, a novel equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels. Preferred implementations define the logical function of bit history in a look up table.
In preferred embodiments, the equalizer converts an input signal, having discrete signal levels at an input data rate, to an output signal having a greater number of discrete signal levels at the input data rate. In particular, the equalizer generates transmitted signal levels based on time since last signal transition. A particularly simple implementation is based on whether a current bit is equal to an immediately previous bit.
The clock rates of circuitry can be reduced by multiplexing outputs of parallel logic circuits operating on different multiple bit inputs to generate the signal levels. In an adaptive system, the level of equalization in the transmitter can be modified as a function of signals detected at the receiver.
BRIEF DESCRIPTION OF THE DRAWINGSThe foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
A description of preferred embodiments of the invention follows.
The density and speed of modern VLSI technology can be applied to overcome the I/O bottleneck they have created by building sophisticated I/O circuitry that compensates for the characteristics of the physical interconnect and cancels dominant sources of timing and voltage noise. Such optimized I/O circuitry is capable of achieving I/O rates an order of magnitude higher than those commonly used today while operating at lower power levels.
A system embodying the invention can achieve a four Gbps signaling rate using 0.5 μm CMOS circuits by controlling and compensating for characteristics of the transmission medium, by cancelling timing skew, and through careful management of time and voltage noise.
The availability of 4 Gbps electrical signaling will enable the design of low-cost, high-bandwidth digital systems. The wide, slow buses around which many contemporary digital systems are organized can be replaced by point-to-point networks using a single, or at most a few, high-speed serial channels resulting in significant reduction in chip and module pinouts and in power dissipation. A network based on 400 MBytes/s serial channels, for example, has several times the bandwidth of a 133 MBytes/s PCI-bus that requires about 80 lines. Also, depending on its topology, the network permits several simultaneous transfers to take place at full rate. A group of eight parallel channels would provide sufficient bandwidth (3.2 GBytes/s) for the CPU to memory connection of today's fastest processors. For modest distances (up to 30 m with 18 AWG wire), high-speed electrical signaling is an attractive alternative to optical communication in terms of cost, power, and board area for peripheral connection and building-sized local-area networks.
Frequency-Dependent Attenuation Causes Intersymbol Interference
Skin-effect resistance causes the attenuation of a conventional transmission line to increase with frequency. With a broadband signal, as typically used in digital systems, the superposition of unattenuated low-frequency signal components with attenuated high-frequency signal components causes intersymbol interference that degrades noise margins and reduces the maximum frequency at which the system can operate.
This effect is most pronounced in the case of a single 1 (0) in a field of 0s (1s) as illustrated in
The problem here is not the magnitude of the attenuation, but rather the interference caused by the frequency-dependent nature of the attenuation. The high-frequency pulse has sufficient amplitude at the receiver for proper detection. It is the offset of the pulse from the receiver threshold by low-frequency interference that causes the problem. Later, we will see how using a transmitter equalizer to preemphasize the high-frequency components of the signal eliminates this problem. However, first we will characterize the nature of this attenuation in more detail.
FIGS. 3A-D show the resistance per meter and the attenuation per meter as a function of frequency for a 30 AWG (d=128 mm) twisted pair with a differential impedance of 100 ohms (
The effect of frequency dependent attenuation is graphically illustrated in the eye-diagrams of
The waveform of
Preemphasizing Signal Transitions Equalizes Line Attenuation
Equalization eliminates the problem of frequency-dependent attenuation by filtering the transmitted or received waveform so the concatenation of the equalizing filter and the transmission line gives a flat frequency response. With equalization, an isolated 1 (0) in a field of 0s (1s) crosses the receiver threshold at the midpoint of its swing, as shown in
We equalize the line using a 4 GHz FIR filter built into the current-mode transmitter. The arrangement is similar to the use of Tomlinson precoding in a narrowband modem (Tomlinson, M., “New Automatic Equalizer Employing Modulo Arithmetic,” Electronic Letters, March 1971). In a high-speed digital system it is much simpler to equalize at the transmitter than at the receiver, as is more commonly done in communication systems. Equalizing at the transmitter allows us to use a simple receiver that just samples a binary value at 4 GHz. Equalizing at the receiver would require an A/D of at least a few bits resolution or a high-speed analog delay line, both difficult circuit design problems. A discrete-time FIR equalizer is preferable to a continuous-time passive or active filter as it is more easily realized in a standard CMOS process.
After much experimentation we have selected a five-tap FIR filter that operates at the bit rate. The weights are trained to match the filter to the frequency response of the line as described below. For a I m 30AWG line, the impulse response is shown in
As shown in FIGS. 6A-C, this filter cancels the low-pass attenuation of the line giving a fairly flat response over the frequency band of interest (the decade from 200 MHz to 2 GHz). We band-limit the transmitted signal via coding to eliminate frequencies below 200 MHz. The equalization band is limited by the length of the filter. Adding taps to the filter would widen the band. We have selected five taps as a compromise between bandwidth and cost of equalization.
Circuit Implementations
Preferred implementations of the invention include finite input response (FIR) filters, and
As in a conventional FIR filter, the input Di is delayed in successive delay elements 28. However, rather than weighting the individual delayed signals and summing the weighted signals to obtain the desired output, the delayed signals are applied to a 5-to-32 decoder 32.
One of the 32 output bits from the decoder 32 is high with any input state and that high bit addresses a 4 bit word from the 32×4 random access memory 34. The memory 34 is shown to be random access in order to allow for reprogramming of the equalization using a training process below. However, the system may be a fixed design which can be implemented using a read only memory.
The 4 bit output from RAM 34 defines one of the 15 output levels generated by a digital-to-analog converter 36 and applied to the transmission line 38. Those levels include 0, seven positive levels where Dout− is pulled low, and seven negative levels where Dout+ is pulled low. To simplify the implementation, each FIR filter is approximated by a transition filter implemented with a look-up table as illustrated in
While the transition filter is a non-linear element, it closely approximates the response of an FIR filter for the impulse functions needed to equalize typical transmission lines. Making this approximation greatly reduces the size and delay of the filter as a 96-bit RAM would be required to implement a full 5-tap FIR filter via a lookup table and the gates 46 and 48.
The transition filter can be simplified even further to the simple logic circuit of
In yet another two-tap embodiment, with a transition, full current drive is used in opposite directions on both sides of the transition. When the signal value remains unchanged, an attenuated current drive is used.
The circuit design of the DAC used in the
Each of the three differential pulse generators is implemented as shown in
To enable operation of the equalization circuit at rates in the order of gigahertz while using circuitry operating only in the order of hundreds of megahertz, the preferred embodiment generates the signal levels by multiplexing outputs of parallel logic circuits operating on different multiple bit inputs.
A block diagram of the multiplexed transmitter is shown in
A training sequence may be used to initialize the transmitter pre-emphasis filter at powerup. Training is performed under the control of a supervisory processor 26 that interfaces with the transmitter on one end of the line and the receiver on the other end via a low-speed serial scan chain. A preliminary version of a training sequence for one channel is as follows:
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- 1. The frequency response of the line is measured. The transmitter is commanded to turn off precompensation and send an alternating sequence of 1s and 0s. The receiver measures the level of the received signal by using a feedback transmitter to shift the DC operating point of the sense-amplifiers. The process is repeated at other bit rates to trace out the attenuation curve. For example, bit rates of Rmax, Rmax/2, Rmax/3 . . . may be tested.
- 2. Based on the attenuation measurements taken in (1), the transmitter equalization is set by programming the FIR filter and/or DAC.
Conclusion
Transmitter equalization extends the data rates and distances over which electronic digital signaling can be reliably used. Preemphasizing the high-frequency components of the signal compensates for the low-pass frequency response of the package and transmission line. This prevents the unattenuated low-frequency components from interfering with high-frequency pulses by causing offsets that prevent detection. With equalization an isolated pulse at the receiver has the same amplitude as a long string of repeated bits. This gives a clean received signal with a good eye opening in both the time and voltage dimensions.
In one embodiment, we implement equalization for a 4 Gbs signaling system by building a 4 GHz, five-tap FIR filter into the transmitter. This filter is simple to implement yet equalizes the frequency response to within 5% across the band of interest. The filter is realized using 0.5 mm CMOS circuitry operating at 400 MHz using a bank of 10 filters and DACs sequenced by a 10-phase 400 MHz clock. Narrow drive periods are realized using series gating to combine two clock phases, an on-phase and off-phase, in each DAC. We have simulated extracted layout of the equalized transmitter driving a load through package parasitics and 1 m of differential strip guide to demonstrate the feasibility of this approach.
The equalizing transmitter described here is one component of a 4 Gbs signaling system we are currently developing for implementation in an 0.5 μm CMOS technology. The system also relies on low-jitter timing circuitry, automatic per-line skew compensation, a narrow-aperture receive amplifier, and careful package design.
The availability of 4 Gbs serial channels in a commodity CMOS technology will enable a range of system opportunities. The ubiquitous system bus can be replaced by a lower-cost yet higher-speed point-to-point network. A single hub chip with 32 serial ports can directly provide the interconnection for most systems and can be assembled into more sophisticated networks for larger systems. A single 4 Gbs serial channel provides adequate bandwidth for most system components and multiple channels can be ganged in parallel for higher bandwidths.
A 4 Gbs serial channel can also be used as a replacement technology at both the component and system level. At the component level, a single serial channel (two pins) replaces 40 100 MHz pins. A 4 GByte/s CPU to L2 cache interface, for example, could be implemented with just eight serial channels. At the system level, high-speed electrical serial channels are a direct replacement for expensive optical interconnect. Using 18 AWG wire, these channels will operate up to lengths of 10 m enabling high-bandwidth, low-cost peripheral connections and local-area networks. Inexpensive electrical repeaters can be used to operate over substantially longer distances.
Even with 4 Gbs channels, system bandwidth remains a major problem for system designers. On-chip logic bandwidth (gates×speed) is increasing at a rate of 90% per year (60% gates and 20% speed). The density and bandwidth of system interconnect is increasing at a much slower rate of about 20% per year as they are limited by mechanical factors that are on a slower growth curve than that of semiconductor lithography. A major challenge for designers is to use scarce system interconnect resources effectively, both through the design of sophisticated signaling systems that use all available wire bandwidth and through system architectures that exploit locality to reduce the demands on this bandwidth.
While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims
1. A circuit comprising:
- a semiconductor chip;
- a transmitter circuit disposed on the chip, the transmitter circuit being operative to accept a digital input signal including a plurality of bits and send an output signal including a series of output current pulses, each bit of the digital input signal being represented by a single output current pulse, each output current pulse having a magnitude which is a function of the digital value of the bit represented by such output current pulse and of the digital values of one or more bits represented by one or more preceding output current pulses, the magnitude of each output current pulse being selected from plural possible magnitudes associated with the digital value of the bit represented by such output current pulse.
2. The circuit as claimed in claim 1 wherein output current pulses representing bits with digital values differing from the digital values of bits represented by a number of preceding output current pulses have greater magnitudes than output current pulses representing bits having digital values which are the same as the digital values of bits represented by the number of preceding output current pulses.
3. The circuit as claimed in claim 1 wherein each output current pulse has:
- (i) a first magnitude when the bit represented by that output current pulse has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output current pulse; and
- (ii) a second magnitude when the bit represented by that output current pulse has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output current pulse;
- the first magnitude being lower than the second magnitude.
4. The circuit as claimed in claim 1 wherein the transmitter circuit includes a plurality of current generators coupled to a common output.
5. The circuit as claimed in claim 4 wherein the transmitter circuit includes a circuit operative to select one or more of the current pulse generators and activate only the selected current pulse generators to provide each output current pulse.
6. The circuit as claimed in claim 4 wherein different ones of the plurality of current pulse generators are arranged to provide currents of different magnitudes.
7. The circuit as claimed in claim 4 wherein the common output includes a pair of output connections for connection to two conductors of a differential transmission line.
8. The circuit as claimed in claim 7 wherein each of the current pulse generators includes a current source, a first control element connected between one of the pair of output connections and the current source, a second control element being connected between the other one of the pair of output connections and the current source, each control element being operable to selectively block or permit flow of current.
9. Data processing equipment comprising a circuit as claimed in claim 7, a differential transmission line coupled to the pair of output connections of the circuit, and a receiver circuit having a pair of input connections, the receiver circuit being operative to detect current pulses on the differential transmission line and convert the current pulses to digital values.
10. Data processing equipment as claimed in claim 9 further comprising a cabinet, wherein the circuit, the receiver circuit and the transmission line are disposed within the cabinet.
11. Data processing equipment comprising a circuit as claimed in claim 1, a transmission line coupled to the transmitter circuit, and a receiver circuit coupled to the transmission line, the receiver circuit being operative to detect current pulses on the transmission line and convert the current pulses to digital values.
12. Data processing equipment as claimed in claim 11 further comprising a cabinet, wherein the circuit, the receiver circuit and the transmission line are disposed within the cabinet.
13. The circuit as claimed in claim 1 further comprising a memory, the transmitter circuit being coupled to the memory to accept the digital input signal from the memory.
14. The circuit as claimed in claim 1 further comprising a processor, the transmitter circuit being coupled to the processor to accept the digital input signal from the processor.
15. The circuit as claimed in claim 1 further comprising a peripheral device, the transmitter circuit being coupled to the peripheral device to accept the digital input signal from the peripheral device.
16. Data processing equipment comprising a plurality of elements selected from the group consisting of processors, memories, and peripheral devices, at least one local signal path for conveying information between the elements, and at least one circuit as claimed in claim 1, the transmitter circuit being coupled to one of the elements for acceptance of the digital input signal from that one of the elements and being coupled to the local signal path for transmission of the current pulses along the local signal path to another one of the elements.
17. Data processing equipment as claimed in claim 16 wherein the transmitter circuit is operable to provide the current pulses with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.
18. A method of sending information comprising the steps of:
- (a) accepting a digital input signal including a plurality of bits at a transmitter circuit within a semiconductor chip; and
- (b) sending a series of output current pulses from the transmitter circuit, each bit of the digital input signal being represented by a single output current pulse, each output current pulse having a magnitude which is a function of the digital value of the bit represented by such output current pulse and of the digital values of one or more bits represented by one or more preceding output current pulses, the magnitude of each output current pulse being selected from plural possible magnitudes associated with the digital value of the bit represented by such output current pulse.
19. The method as claimed in claim 18 wherein output current pulses representing bits with digital values differing from the digital values of bits represented by a number of preceding output current pulses have greater magnitudes than output current pulses representing bits having digital values which are the same as the digital values of bits represented by the number of preceding output current pulses.
20. The method as claimed in claim 18 wherein each output current pulse has:
- (i) a first magnitude when the bit represented by that output current pulse has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output current pulse; and
- (ii) a second magnitude when the bit represented by that output current pulse has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output current pulse;
- the first magnitude being lower than the second magnitude.
21. The method as claimed in claim 18 wherein the step of sending the output current pulses includes actuating one or more of a plurality of current generators to send currents through a common output to form each output current pulse.
22. The method as claimed in claim 18 wherein the step of sending the output current pulses includes sending the pulses on a differential transmission line.
23. The method as claimed in claim 22 wherein the step of sending the pulses on the differential transmission line includes actuating one or more current sources and actuating control elements connected between the current sources and the transmission line to steer current passing through each of the one or more current sources to one conductor of the differential transmission line.
24. The method as claimed in claim 18 wherein the step of sending the output current pulses includes sending the output current pulses along a local signal path of a digital system.
25. The method as claimed in claim 24 wherein the steps of accepting the digital input signal and sending the output current pulses convey information between two or more elements of the digital system selected from the group consisting of processors, memories, and peripheral devices.
26. The method as claimed in claim 18 wherein the output current pulses constitute an output signal having a frequency of at least 1 GHz and a bandwidth greater than 100 MHz.
27. A circuit comprising:
- a semiconductor chip;
- a transmitter circuit disposed on the chip, the transmitter circuit being operative to accept a digital input signal including a plurality of bits and send an output signal including a series of output bit signals, each such output bit signal representing one bit of the digital input signal, each output bit signal having a signal level which is a function of the digital value represented by such output bit signal and the digital values of the bits represented by one or more preceding output bit signals so that an output bit signal representing a bit having a digital value different from digital values of bits represented by the one or more preceding output bit signals will have a signal level of greater magnitude than an output bit signal representing a bit having the same digital value as the digital values of the bits represented by the one or more output bit signals, the transmitter circuit including an output connection, the transmitter circuit being operative to send the output bit signals in nonmodulated form through the-output connection, and the transmitter circuit being operable to provide the output signal with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.
28. The circuit as claimed in claim 27 wherein the signal level of each output bit signal has:
- (i) a first magnitude when the bit represented by that output bit signal has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output bit signal; and
- (ii) a second magnitude when the bit represented by that output bit signal has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output bit signal;
- the first magnitude being lower than the second magnitude.
29. Data processing equipment comprising a circuit as claimed in claim 27, a transmission line coupled to the transmitter circuit, and a receiver coupled to the transmission line, the transmitter circuit being operative to send the output bit signals in nonmodulated form on the transmission line.
30. Data processing equipment as claimed in claim 29 further comprising a cabinet, wherein the circuit, the receiver and the transmission line are disposed within the cabinet.
31. The circuit as claimed in claim 27 further comprising a memory, the transmitter circuit being coupled to the memory to accept the digital input signal from the memory.
32. The circuit as claimed in claim 27 further comprising a processor, the transmitter circuit being coupled to the processor to accept the digital input signal from the processor.
33. The circuit as claimed in claim 27 further comprising a peripheral device, the transmitter circuit being coupled to the peripheral device to accept the digital input signal from the peripheral device.
34. Data processing equipment comprising a plurality of elements selected from the group consisting of processors, memories, and peripheral devices, at least one local signal path for conveying information between the elements, and at least one circuit as claimed in claim 27, the transmitter circuit being coupled to one of the elements to accept the digital input signal from such element and being coupled to the local signal path for transmission of the output signal along the local signal path to another one of the elements.
35. A method of sending information comprising the steps of:
- (a) accepting a digital input signal including a plurality of bits at a transmitter circuit within a semiconductor chip; and
- (b) sending an output signal including a series of output bit signals in nonmodulated form from the transmitter circuit to a receiver circuit, each such output bit signal representing one bit of the digital input signal, each output bit signal having a signal level which is a function of the digital value of the bit represented by such output bit signal and of the digital values of the bits represented by one or more preceding output bit signals so that an output bit signal representing a bit having a digital value different from digital values of bits represented by the one or more preceding output bit signals will have a signal level of greater magnitude than an output bit signal representing a bit having the same digital value as the bits represented by the digital values of the one or more preceding output bit signals, the output signal having an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.
36. The method as claimed in claim 35 wherein the signal level of each output bit signal has:
- (i) a first magnitude when the bit represented by that output bit signal has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output bit signal; and
- (ii) a second magnitude when the bit represented by that output bit signal has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output bit signal;
- the first magnitude being lower than the second magnitude.
37. The method as claimed in claim 35 wherein the step of sending the output signal includes sending the output current pulses along a local signal path of a digital system to the receiver circuit.
38. The method as claimed in claim 37 wherein the steps of accepting the digital input signal and sending the output signal convey information between two or more elements of the digital system selected from the group consisting of processors, memories, and peripheral devices.
Type: Application
Filed: Jul 10, 2006
Publication Date: Dec 14, 2006
Inventor: William Dally (Stanford, CA)
Application Number: 11/483,971
International Classification: H04L 25/03 (20060101);