Abstract: A mixing signal processing technique modifies digital audio recordings to simulate the linear and nonlinear effects of propagation and mixing of sounds in air. When multiple sounds or complex sounds comprised of multiple frequencies in the audible spectrum propagate in such a nonlinear medium, they transfer energy into sound at new frequencies given by the sums and differences of the original signal frequencies. The mixing signal processing technique may improve the ability of a system to reproduce the effects of a live performance using a digital audio recording.

Abstract: A priming signal processing technique modifies digital audio recordings to reduce the stress experienced by a listener's auditory system. A priming signal may reduce the instantaneous stress experienced by the auditory system during sudden changes in signal energy. The priming signal may leverage the temporal auditory masking, such that pre-signal priming additions may not result in obvious differences in perceived sounds.

Abstract: A motion signal processing technique modifies digital audio recordings in order to restore a sense of motion, liveliness, and spatial dynamics. The technique compensates for the static presentation of sound created by modern recording and sound synthesis techniques and common modern playback equipment such as headphones and ear buds in order to create a more natural, immersive, and enjoyable listening experience.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

Abstract: A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.

Abstract: A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.

Abstract: A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.

Abstract: In one embodiment, a galvanometer may include a moving magnet rotor. The moving magnet rotor may include an opening in each end. An output shaft and a tail shaft may be received in respective opening in the moving magnet rotor. The output shaft and tail shaft may formed from a material having a high stiffness to strength ratio, such as a ceramic material.

Abstract: A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system bus, a memory, a plurality of I/O components and an I/O processor. The data processing system further comprises operational protocol providing a pair of instructions/commands that are utilized to complete a DMA Write operation. The pair of instructions is DMA_Write_No_Data and DMA_Write With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire “DMA ownership” of a cache line that is to be written. The initial ownership of the cache line is marked by a weak DMA state (D1), which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations.

Abstract: A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands that are utilized to complete a DMA Write operation. The instructions are DMA_Write_No_Data and DMA_Write_With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire ownership of a cache line that is to be written. The ownership of the cache line is marked by a weak DMA state, which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations. When each preceding DMA Write operation has completed or each corresponding DMA_Write_No_Data operation has been placed in a DMA Exclusive state, then the weak DMA state is changed to a DMA Exclusive state, which forces a retry of snooped operations until the write transaction to memory is completed.

Abstract: A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands that are utilized to complete a DMA Write operation. The instructions are DMA_Write_No_Data and DMA_Write_With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire ownership of a cache line that is to be written. The ownership of the cache line is marked by a weak DMA state, which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations. When each preceding DMA Write operation has completed or each corresponding DMA_Write_No_Data operation has been placed in a DMA Exclusive state, then the weak DMA state is changed to a DMA Exclusive state, which forces a retry of snooped operations until the write transaction to memory is completed.

Abstract: A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system bus, a memory, a plurality of I/O components and an I/O processor. The data processing system further comprises operational protocol providing a pair of instructions/commands that are utilized to complete a DMA Write operation. The pair of instructions is DMA_Write_No_Data and DMA Write With_Data. DMA_Write_No Data is an address-only operation on the system bus that is utilized to acquire “DMA ownership” of a cache line that is to be written. The initial ownership of the cache line is marked by a weak DMA state (D1), which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations.

Abstract: A rotary drum cooler for cooling particulate material (e.g. coke particles) having at least one cooling pocket which, in turn, includes a flexible vent pipe assembly which can slide in relation to the shell of the cooler. By making the vent pipe slidable, it can move in response to the expansion and contraction of the pocket within the shell. The vent pipe assembly is comprised of (a) a tube which is connected to the pocket and which slidably extends through an aperture in the shell and (b) a flexible means for sealingly connecting the outer end of the tube to the shell.

Abstract: Open-topped container for cultivating one or more plants individually contained in a corresponding number of cavities of said container, containing a natural or artificial cultivating medium for said plant(s), e.g. soil, and being adapted for easy transplantation of such plants by said base comprising a peripheral line of weakness adapted for an application of pressure against the base cause the base to break loose from the remainder of the container. The line of weakness having an average breaking strength of between 10 and 40% of the average breaking strength of the base is preferably formed wholly or in part by elongate drainage holes passing through the base and so dimensioned that cultivating medium is retained. For transplantation the base is pushed upwards with the cultivating medium and plant.