Abstract: A method of tracking instruction dependency in a processor issuing instructions speculatively includes recording in an instruction dependency array (IDA) an entry for each instruction that indicates data dependencies, if any, upon other active instructions. An output vector read out from the IDA indicates data readiness based upon which instructions have previously been selected for issue. The output vector is used to select and read out issue-ready instructions from an instruction buffer.

Abstract: A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming sc

Abstract: An SMT system has a dynamically shared GCT. Performance for the SMT is improved by configuring the GCT to allow an instruction group from each thread to complete simultaneously. The GCT has a read port for each thread corresponding to the completion table instruction/address array for simultaneous updating on completion. The forward link array also has a read port for each thread to find the next instruction group for each thread upon completion. The backward link array has a backward link write port for each thread in order to update the backward links for each thread simultaneously. The GCT has independent pointer management for each thread. Each of the threads has simultaneous commit of their renamed result registers and simultaneous updating of outstanding load and store tag usage.

Abstract: The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared dispatch pipeline are flushed in response to resource requirements. A first thread in an SMT may be using more processing than corresponds to its priority because its instructions are dominating use of a shared resource. In this case, to rebalance instruction dispatch between the first thread and the second thread, a dispatch flush of instructions of the first thread is issued. Normally the flushed instructions of a thread are refetched and reenter the dispatch pipeline. If the first thread is dominating use of shared resources, hold may be issued following the dispatch flush holding instructions of the first thread until a balanced utilization is realized.

Abstract: A computer implemented method, apparatus, and computer usable program code are provided for implementing a set of architected register files as a set of temporary rename buffers. An instruction dispatch unit receives an instruction that includes instruction data. The instruction dispatch unit determines a thread mode under which a processor is operating. Responsive to determining the thread mode, the instruction dispatch unit determines an ability to use the set of architected register files as the set of temporary rename buffers. Responsive to the ability to use the set of architected register files as the set of temporary rename buffers, the instruction dispatch unit analyzes the instruction to determine an address of an architected register file in the set of architected register files where the instruction data is to be stored. The architected register file operating as a temporary rename buffer stores the instruction data as finished data.

Abstract: A method for dependency tracking and flush recovery for an out-of-order processor includes recording, in a last definition (DEF) data structure, an identifier of a first instruction as the most recent instruction in an instruction sequence that defines contents of the particular logical register and recording, in a next DEF data structure, the identifier of the first instruction in association with an identifier of a previous second instruction also indicating an update to the particular logical register. In addition, a recovery array is updated to indicate which of the instructions in the instruction sequence updates each of the plurality of logical registers. In response to misspeculation during execution of the instruction sequence, the processor performs a recovery operation to place the identifier of the second instruction in the last DEF data structure by reference to the next DEF data structure and the recovery array.

Abstract: A method and processor for performing on-demand scratch register reallocation by dynamically adjusting the number of scratch registers from within the pool of rename registers includes initially allocating from a set of physical registers one or more architected registers and a pool of one or more rename registers and allocating from the pool of rename registers an initial number of scratch registers for storing microcode operands. In response to detecting that a fetched instruction requires an additional scratch register beyond the initial number, a selected physical register is reallocated from among the pool of rename registers as the additional scratch register, and a flag is set to indicate the rename register is allocated as the additional scratch register. In response to determining that the additional scratch register is no longer needed, the additional scratch register is deallocated and the flag is reset, such that the selected physical register returns to the pool of rename registers.

Abstract: An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses a special form of a “no operation” (NOP) instruction (hereafter termed thread priority NOP). When the thread priority NOP is dispatched, its special NOP is decoded in the decode unit of the IDU into an operation that writes a special code into the completion table for the thread priority NOP. A “trouble” bit is also set in the completion table that indicates which instruction group contains the thread priority NOP. The trouble bit indicates that special processing is required after instruction completion. The thread priority instruction is processed after completion using the special code to change a thread's priority.

Abstract: A method and processor for performing on-demand scratch register reallocation by dynamically adjusting the number of scratch registers from within the pool of rename registers includes initially allocating from a set of physical registers one or more architected registers and a pool of one or more rename registers and allocating from the pool of rename registers an initial number of scratch registers for storing microcode operands. In response to detecting that a fetched instruction requires an additional scratch register beyond the initial number, a selected physical register is reallocated from among the pool of rename registers as the additional scratch register, and a flag is set to indicate the rename register is allocated as the additional scratch register. In response to determining that the additional scratch register is no longer needed, the additional scratch register is deallocated and the flag is reset, such that the selected physical register returns to the pool of rename registers.

Abstract: A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming sc

Abstract: The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared dispatch pipeline are flushed in response to resource requirements. An exception condition detected in one thread can be resolved by issuing a following instruction for that thread. Until the exception condition is resolved, resources are not released that allow the second thread to dispatch which in turn prevents dispatch from the first thread to resolve the exception condition. A flush of the first thread is not issued to resolve the stall. Instead, a dispatch flush of the second thread is issued. If a second thread instruction has long latency resource requirements that prevent the first thread from dispatching to resolve the exception, then a hold is issued controlling when the second thread instruction is refetched.

Abstract: A methodology to process flushes in an SMT processor with a dynamically shared group completion table (GCT) and a Flush table comprises identification of incoming flush sources by thread. This uses the forward link array by flush source to determine the next instruction group following the group indicated by the flush source (for example, for mispredicts and load/store flush-next type flushes). Presentation of flush completion table entry numbers or instruction group identifiers (Gtags) to the flush table for computation of oldest flushed group tag corresponding to each thread. The flush selection cycle wherein the flush table outputs are compared against saved versions of all the flush Gtags presented to determine which flush source matches the oldest group output from the flush table. The flush source information is used with the selected oldest Gtag to determine the appropriate additional flushing action to take during the flush cycle.

Abstract: The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared dispatch pipeline are flushed in response to resource requirements. A first thread in an SMT may be using more processing than corresponds to its priority because its instructions are dominating use of a shared resource. In this case, to rebalance instruction dispatch between the first thread and the second thread, a dispatch flush of instructions of the first thread is issued. Normally the flushed instructions of a thread are refetched and reenter the dispatch pipeline. If the first thread is dominating use of shared resources, hold may be issued following the dispatch flush holding instructions of the first thread until a balanced utilization is realized.

Abstract: A method and multithreaded processor for dynamically sharing an interrupt handling logic unit among multiple threads. A first and second state unit may be configured to determine whether an interrupt was generated from a first thread and a second thread, respectively. An arbiter may be coupled to the first and second state units. A shared interrupt handling logic unit may be coupled to the arbiter where the shared interrupt handling logic unit may be configured to handle interrupts generated from the first and second threads. Upon a state unit, e.g., first state unit, second state unit, determining an interrupt was generated from a particular thread, the state unit may request control of the interrupt handling logic unit from the arbiter. The arbiter may grant the request from the state unit if the interrupt handling logic unit is available to handle the interrupt detected.

Abstract: An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses a special form of a “no operation” (NOP) instruction (hereafter termed thread priority NOP). When the thread priority NOP is dispatched, its special NOP is decoded in the decode unit of the IDU into an operation that writes a special code into the completion table for the thread priority NOP. A “trouble” bit is also set in the completion table that indicates which instruction group contains the thread priority NOP. The trouble bit indicates that special processing is required after instruction completion. The thread priority instruction is processed after completion using the special code to change a thread's priority.

Abstract: The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared dispatch pipeline are flushed in response to resource requirements. An exception condition detected in one thread can be resolved by issuing a following instruction for that thread. Until the exception condition is resolved, resources are not be released allowing the second thread to dispatch which in turn prevents dispatch from the first thread to resolve the exception condition. A flush of the first thread is not issued to resolve the stall rather a dispatch flush of the second thread is issued. If a second thread instruction has long latency resource requirements that prevent the first thread from dispatching to resolve the exception, then a hold is issued controlling when the second thread instruction is refetched.

Abstract: A methodology to process flushes in an SMT processor with a dynamically shared group completion table (GCT) and a Flush table comprises identification of incoming flush sources by thread. This uses the forward link array by flush source to determine the next instruction group following the group indicated by the flush source (for example, for mispredicts and load/store flush-next type flushes). Presentation of flush completion table entry numbers or instruction group identifiers (Gtags) to the flush table for computation of oldest flushed group tag corresponding to each thread. The flush selection cycle wherein the flush table outputs are compared against saved versions of all the flush Gtags presented to determine which flush source matches the oldest group output from the flush table. The flush source information is used with the selected oldest Gtag to determine the appropriate additional flushing action to take during the flush cycle.

Abstract: An SMT system has a dynamically shared GCT. Performance for the SMT is improved by configuring the GCT to allow an instruction group from each thread to complete simultaneously. The GCT has a read port for each thread corresponding to the completion table instruction/address array for simultaneous updating on completion. The forward link array also has a read port for each thread to find the next instruction group for each thread upon completion. The backward link array has a backward link write port for each thread in order to update the backward links for each thread simultaneously. The GCT has independent pointer management for each thread. Each of the threads has simultaneous commit of their renamed result registers and simultaneous updating of outstanding load and store tag usage.

Abstract: A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.

Abstract: A system and method for checking the test logic contained in a computer memory system during POST such that any errors can be determined and made available to the system software prior to beginning processing operations. Single and double bit errors are induced which the ECC logic must identify and correct. The CPU compares the data that is written to memory with the data that is read back. Thus, since it is known that an error occurred, due to the induced error provided by the present invention, identical data will verify that the ECC correction logic is working properly. More specifically, a multiplexer is provided in the data write path which substitutes a constant set of identical bits for the actual data generated by the CPU. ECC bits are generated based on the actual generated test data, rather than the inserted identical bits. The substituted data bits and generated ECC bits are then stored in memory. An error condition is identified when the data and ECC code is read back from memory.