Patents by Inventor William E. Hoke

William E. Hoke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180286954
    Abstract: A structure having: a nucleation layer; and a Group III-Nitride structure disposed on a surface of the nucleation layer, the Group III-Nitride structure comprising a plurality of pairs of stacked Group III-Nitride layers, each one of the pairs of layers having a lower layer having a 3D growth structure and each one of the upper one of the pairs of layers having a 2D growth structure. Each one of the lower layers at completion has a surface roughness greater than a surface roughness at completion of an upper one of the pair of layers. Interfaces between each one of the upper layers and each one of the lower layers of the plurality of pairs of stacked Group III-Nitride layers have crystallographic dislocation combinations and/or annihilations therein.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Applicant: Raytheon Company
    Inventors: Brian D. Schultz, Theodore D. Kennedy, Amanda Kerr, William E. Hoke
  • Patent number: 9419125
    Abstract: A semiconductor structure having a Group III-N buffer layer and a Group III-N barrier layer in direct contact to form a junction between the Group III-V buffer layer the Group III-N barrier layer producing a two dimensional electron gas (2DEG) channel, the Group III-N barrier layer having a varying dopant concentration. The lower region of the Group III-N barrier layer closest to the junction is void of intentionally introduced dopant and a region above the lower region having intentionally introduced, predetermined dopant with a predetermined doping concentration above 1Ă—1017 atoms per cm3.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: August 16, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Brian D. Schultz, Abbas Torabi, Eduardo M. Chumbes, Shahed Reza, William E. Hoke
  • Patent number: 9293379
    Abstract: A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: March 22, 2016
    Assignee: Raytheon Company
    Inventors: Eduardo M. Chumbes, William E. Hoke, Kelly P. Ip, Dale M. Shaw, Steven K. Brierley
  • Publication number: 20150059640
    Abstract: A method for depositing a column III-V material over a selected portion of a substrate through a window formed in a dielectric layer disposed over the selected portion of the substrate. The method includes forming a single crystal layer or polycrystalline layer over a field region of the dielectric layer adjacent to the window; and, growing, by MOCVD, column III-V material over the single crystal layer or polycrystalline layer and through the window over the selected portion of the substrate.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: Raytheon Company
    Inventors: Jeffrey R. LaRoche, William E. Hoke, Thomas E. Kazior
  • Patent number: 8823146
    Abstract: A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 2, 2014
    Assignee: Raytheon Company
    Inventor: William E. Hoke
  • Publication number: 20140231870
    Abstract: A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 21, 2014
    Applicant: Raytheon Company
    Inventor: William E. Hoke
  • Patent number: 8772786
    Abstract: A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. In effect, a sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact résistance) all along the contact between the lower semiconductor layer and the electron donor layer.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 8, 2014
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, William E. Hoke, Eduardo M. Chumbes, Kevin McCarthy
  • Publication number: 20140183545
    Abstract: A semiconductor structure having: a first semiconductor layer; and an electric carrier generating layer disposed on the first semiconductor layer to generate electric carriers within the first semiconductor layer by polarization effects, the electric carrier generating layer having a predetermined conduction band and a predetermined valance band, the electric carrier generating layer having a concentration of non-carrier generating contaminants having an energy level, the difference in the energy level of the non-carrier type contaminants and the energy level of either the conduction band or the valence band being greater than 10 kT, where k is Boltzmann's constant and T is the temperature of the electric carrier generating semiconductor layer, the electric carrier generating semiconductor layer being doped with a dopant having an energy level, the difference in the energy level of the dopant and the energy level of either the conduction band or the valence band being greater than 10 kT, the dopant having a c
    Type: Application
    Filed: January 3, 2013
    Publication date: July 3, 2014
    Applicant: Raytheon Company
    Inventor: William E. Hoke
  • Patent number: 8698200
    Abstract: Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium flouride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 15, 2014
    Assignee: Raytheon Company
    Inventors: Daniel P. Resler, William E. Hoke
  • Publication number: 20140014966
    Abstract: A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. In effect, a sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact resistance) all along the contact between the lower semiconductor layer and the electron donor layer.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 16, 2014
    Applicant: Raytheon Company
    Inventors: Kamal Tabatabaie, William E. Hoke, Eduardo M. Chumbes, Kevin McCarthy
  • Patent number: 8575666
    Abstract: A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 5, 2013
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, Thomas E. Kazior, William E. Hoke
  • Publication number: 20130082281
    Abstract: A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Raytheon Company
    Inventors: Jeffrey R. LaRoche, Thomas E. Kazior, William E. Hoke
  • Publication number: 20120299012
    Abstract: Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium flouride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.
    Type: Application
    Filed: August 10, 2012
    Publication date: November 29, 2012
    Applicant: RAYTHEON COMPANY
    Inventors: Daniel P. Resler, William E. Hoke
  • Publication number: 20120300168
    Abstract: An optically transparent electrically conductive structure having: an optically transparent substrate; an optically transparent buffer and barrier layers; a plurality of optically transparent, two-dimensional electron gas (2-DEG) carrier layers disposed on the substrate. A barrier layer is disposed over a corresponding one of the carrier layers. One of the carrier layers comprises: a GaN channel layer and wherein the barrier layer is Al1-xInxN or Al5yGa1-6yInyN where 0.10<x<0.30 and 0.05<y<0.17.
    Type: Application
    Filed: May 23, 2011
    Publication date: November 29, 2012
    Applicant: Raytheon Company
    Inventor: William E. Hoke
  • Publication number: 20120261721
    Abstract: A semiconductor structure having: a column IV material or column IV-IV material; a nucleation layer of AlN layer or a column III nitride having more than 60% aluminum content on a surface of the column IV material or column IV-IV material and a layer of column III-V material over the nucleation layer, where the nucleation layer and the layer of column III-V material over the nucleation layer have different crystallographic structures. In one embodiment, the column III-V nucleation layer is a nitride and the column III-V material of the over the nucleation layer is a non-nitride such as, for example, an arsenide (e.g., GaAs), a phosphide (e.g., InP), or an antimonide (e.g. InSb), or alloys thereof.
    Type: Application
    Filed: April 18, 2011
    Publication date: October 18, 2012
    Applicant: Raytheon Company
    Inventor: William E. Hoke
  • Patent number: 8268707
    Abstract: Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: September 18, 2012
    Assignee: Raytheon Company
    Inventors: Daniel P. Resler, William E. Hoke
  • Patent number: 8212294
    Abstract: A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is <111> and wherein the crystallographic orientation of the silicon layer is <100>. In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the <100> silicon layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: July 3, 2012
    Assignee: Raytheon Company
    Inventors: William E. Hoke, Jeffrey R. LaRoche
  • Publication number: 20110180857
    Abstract: A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is <111> and wherein the crystallographic orientation of the silicon layer is <100>. In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the <100> silicon layer.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 28, 2011
    Applicant: Raytheon Company
    Inventors: William E. Hoke, Jeffrey R. LaRoche
  • Patent number: 7968865
    Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1-x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: June 28, 2011
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, William E. Hoke, Steven D. Bernstein, Ralph Korenstein
  • Publication number: 20110049581
    Abstract: A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 3, 2011
    Applicant: Raytheon Company
    Inventors: Eduardo M. Chumbes, William E. Hoke, Kelly P. Ip, Dale M. Shaw, Steven K. Brierley