Abstract: A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer.

Abstract: Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.

Abstract: Apparatus and method for growing and observing the growth of epitaxial layers on a wafer. The apparatus includes: epitaxial growth apparatus; a source of light mounted to illuminate an entire surface of the wafer in the apparatus during growth of the epitaxial layer on the entire surface of the wafer; and apparatus for observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The method includes growing the epitaxial layer on a surface of the wafer and observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The growing process is varied in accordance with the observation. With an epitaxial layer of gallium nitride (GaN) the entire surface of the wafer is observed for balls of gallium.

Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1-x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.

Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1?x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.

Abstract: A semiconductor structure having: a channel layer having a conductive channel therein; a pair of polarization generating layers; a spacer layer disposed between the pair of polarization generating layers. The polarization generating layers create polarization fields along a common, predetermined direction. Each one of the pair of polarizations layers may be InGaN; InAlGaN; or quaternary InxAlyGa1-x-yN and x is greater than or equal to y/2. The polarization generating layers create polarization fields along a common, predetermined direction constructively increasing the total polarization fields experienced by the channel layer to increase confinement of carriers in the conductive channel.

Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1-x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.

Abstract: Apparatus and method for growing and observing the growth of epitaxial layers on a wafer. The apparatus includes: epitaxial growth apparatus; a source of light mounted to illuminate an entire surface of the wafer in the apparatus during growth of the epitaxial layer on the entire surface of the wafer; and apparatus for observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The method includes growing the epitaxial layer on a surface of the wafer and observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The growing process is varied in accordance with the observation. With an epitaxial layer of gallium nitride (GaN) the entire surface of the wafer is observed for balls of gallium.

Abstract: A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a compound of silicon wherein the first AlN layer is substantially free of silicon.

Abstract: A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InxGa1-xAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InxGa1-xAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

Abstract: A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InxGa1-xAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InxGa1-xAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

Abstract: A semiconductor structure is provided having a III-V substrate, a buffer layer over the substrate, such buffer layer having a compositional graded quaternary lower portion and a compositional graded ternary upper portion. In one embodiment, the lower portion of the buffer layer is compositional graded AlGaInAs and the upper portion is compositional graded AlInAs.

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract: A semiconductor structure is provided having a III-V substrate, a buffer layer over the substrate, such buffer layer having a compositional graded quaternary lower portion and a compositional graded ternary upper portion. In one embodiment, the lower portion of the buffer layer is compositional graded AlGaInAs and the upper portion is compositional graded AlInAs.

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1-xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract: A semiconductor structure, e.g., a high electron mobility transistor structure, is formed by using metamorphic growth and strain compensation. The structure includes a substrate, a graded layer over the substrate, a first donor/barrier layer over the graded layer, and a channel layer over the first donor/barrier layer. The substrate has a substrate lattice constant, and the graded layer has a graded lattice constant. The graded layer has a first lattice constant near a bottom of the graded layer substantially equal to the substrate lattice constant and a second lattice constant near a top of the graded layer different than the first lattice constant. The first donor/barrier layer has a third lattice constant, and the channel layer has a fourth lattice constant. The second lattice constant is intermediate the third and fourth lattice constants.

Abstract: The invention provides a method of fabricating a wafer including growing a single crystal layer comprising a III-V compound in a first chamber at a temperature above 350° C. A temperature of a surface of the single crystal layer is reduced to below about 350° C. in the first chamber. An indium arsenide layer is deposited on the single crystal layer, to form an intermediate structure, in the first chamber at a temperature below 350° C. and above 100° C. The intermediate structure is transferred to a second chamber. A surface of the intermediate structure is heated to a temperature above about 600° C. to remove substantially all of the indium arsenide layer and impurities collected in the indium arsenide layer during the transfer to the second chamber. Another material is deposited on the single crystal layer in the second chamber.

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1-xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1-xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1-yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.