Patents by Inventor William E. Wilson
William E. Wilson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6830875Abstract: A method for forming an electronic structure. Provides is a layer that includes a cylindrical volume of a photoimageable dielectric (PID) material, an annular volume of the PID material circumscribing the cylindrical volume, and a remaining volume of the PID material circumscribing the annular volume. The layer is photolithograhically exposed to radiation. The annular volume is fully cured by the radiation. The remaining volume is partially cured by the remaining volume by said radiation. The method prevents curing of the cylindrical volume, wherein the PID material in the cylindrical volume remains uncured.Type: GrantFiled: October 7, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Stephen J. Fuerniss, Gary Johansson, Ross W. Keesler, John M. Lauffer, Voya R. Markovich, Peter A. Moschak, David J. Russell, William E. Wilson
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Patent number: 6781064Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.Type: GrantFiled: June 29, 1999Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Anilkumar C. Bhatt, James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich, William J. Rudik, William E. Wilson
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Publication number: 20040134685Abstract: A method of forming a printed circuit board with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the board including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.Type: ApplicationFiled: December 22, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
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Patent number: 6750405Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.Type: GrantFiled: October 17, 2000Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
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Publication number: 20040058071Abstract: A colloidal metal seed formulation useful for catalytically activating a surface of a non-conductive dielectric substrate in an electroless plating process is provided. The colloidal metal seed formulation includes stannous chloride, palladium chloride, HCl and a surfactant selected from a diphenyloxide disulfonic acid or alkali or alkaline earth metal salt thereof, C30H50O10, an alcohol alkoxylate and mixtures thereof. A method of electroless plating of a conductive metal onto a non-conductive dielectric substrate using the colloidal metal seed formulation is also provided.Type: ApplicationFiled: September 24, 2002Publication date: March 25, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raymond T. Galasco, Roy H. Magnuson, Voya R. Markovich, Thomas R. Miller, Anita Sargent, William E. Wilson
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Patent number: 6664485Abstract: The present invention provides a printed circuit board and a method for the production of a printed circuit board having fine-line circuitry and greater aspect ratio on a subcomposite with plated through holes. A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.Type: GrantFiled: February 7, 2001Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Anilkumar C. Bhatt, Voya R. Markovich, Irving Memis, William E. Wilson
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Publication number: 20030047357Abstract: A through hole, and associated method of formation, through a layered structure that includes one or more layers having photoimageable dielectric (PID) material. The method forms a via within each such layer in isolation and then stacks the layers in a way that registers the vias over one another such that the through hole is formed as the sequentially registered vias. A sticker layer of the layered structure includes a cylindrical volume, an annular volume circumscribing the cylindrical volume, and a remaining volume surrounding the annular volume. The sticker layer preferentially includes a power plane of continuous metalization having a hole, wherein a perimeter of the hole surrounds the fully cured volume and circumscribes a portion of the remaining volume.Type: ApplicationFiled: October 7, 2002Publication date: March 13, 2003Inventors: Stephen J. Fuerniss, Joan Cangelosi, Gary Johansson, Ross W. Keesler, John M. Lauffer, Voya R. Markovich, Peter A. Moschak, David J. Russell, William E. Wilson
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Patent number: 6521844Abstract: An electronic structure. The electronic structure comprises a layer. The layer includes: a cylindrical volume; a fully cured annular volume of a photoimageable dielectric (PID) material circumscribing the cylindrical volume; and a partially cured remaining volume of the PID material circumscribing the annular volume. The cylindrical volume may include a via. The structure can include a power plane.Type: GrantFiled: October 29, 1999Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Stephen J. Fuerniss, Gary Johansson, Ross W. Keesler, John M. Lauffer, Voya R. Markovich, Peter A. Moschak, David J. Russell, William E. Wilson
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Patent number: 6479093Abstract: A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.Type: GrantFiled: January 31, 2002Date of Patent: November 12, 2002Assignee: International Business Machines CorporationInventors: John M. Lauffer, Voya R. Markovich, Thomas R. Miller, Konstantinos I. Papathomas, William E. Wilson
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Patent number: 6451509Abstract: A method forming a composite laminate structure includes providing first and second circuit board element each having circuitry on at least one face thereof and plated through holes. A voltage plane element is provided having at least one voltage plane having opposite faces with layers of partially cured photodielectric material on each face. At least one hole is photopatterned and etched through the voltage plane element but completely isolated from the voltage plane. Each through hole in the voltage plane element is aligned with a plated through hole in each of the circuit board elements to provide a surface on the voltage plane element communicating with the plated through holes. The voltage plane is laminated between the circuit board elements and the photoimageable material on the voltage plane is fully cured.Type: GrantFiled: January 2, 2001Date of Patent: September 17, 2002Assignee: International Business Machines CorporationInventors: Ross W. Keesler, Voya R. Markovich, Jim P. Paoletti, Marybeth Perrino, William E. Wilson
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Publication number: 20020098331Abstract: A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.Type: ApplicationFiled: January 31, 2002Publication date: July 25, 2002Applicant: International Business Machines CorporationInventors: John M. Lauffer, Voya R. Markovich, Thomas R. Miller, Konstantinos I. Papathomas, William E. Wilson
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Patent number: 6418616Abstract: A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.Type: GrantFiled: February 28, 2001Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: Anilkumar C. Bhatt, Voya R. Markovich, Irving Memis, William E. Wilson
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Patent number: 6388204Abstract: A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.Type: GrantFiled: August 29, 2000Date of Patent: May 14, 2002Assignee: International Business Machines CorporationInventors: John M. Lauffer, Voya R. Markovich, Thomas R. Miller, Konstantinos I. Papathomas, William E. Wilson
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Publication number: 20010023044Abstract: A method forming a composite laminate structure includes providing first and second circuit board element each having circuitry on at least one face thereof and plated through holes. A voltage plane element is provided having at least one voltage plane having opposite faces with layers of partially cured photodielectric material on each face. At least one hole is photopatterned and etched through the voltage plane element but completely isolated from the voltage plane. Each through hole in the voltage plane element is aligned with a plated through hole in each of the circuit board elements to provide a surface on the voltage plane element communicating with the plated through holes. The voltage plane is laminated between the circuit board elements and the photoimageable material on the voltage plane is fully cured.Type: ApplicationFiled: January 2, 2001Publication date: September 20, 2001Inventors: Ross W. Keesler, Voya R. Markovich, Jim P. Paoletti, Marybeth Perrino, William E. Wilson
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Publication number: 20010009066Abstract: A method provides for additive platinum on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.Type: ApplicationFiled: February 28, 2001Publication date: July 26, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anilkumar C. Bhatt, Voya R. Markovich, Irving Memis, William E. Wilson
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Patent number: 6264851Abstract: The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.Type: GrantFiled: March 17, 1998Date of Patent: July 24, 2001Assignee: International Business Machines CorporationInventors: Voya R. Markovich, William E. Wilson, Michael Wozniak
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Publication number: 20010007289Abstract: A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.Type: ApplicationFiled: February 7, 2001Publication date: July 12, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anilkumar C. Bhatt, Voya R. Markovich, Irving Memis, William E. Wilson
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Patent number: 6204453Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.Type: GrantFiled: December 2, 1998Date of Patent: March 20, 2001Assignee: International Business Machines CorporationInventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
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Patent number: 6204456Abstract: Methods of filling apertures, for example, through holes, in substrates are provided. The methods utilize a dielectric film, preferably a photoimageable dielectric film, which is employed to fill the apertures and to form a dielectric film disposed above the substrate at the same time. As a result, the aperture fill material is the same as, and indeed continuous with, the dielectric film which is disposed on the substrate. The method employs the following steps: providing a substrate having apertures; providing a dielectric film disposed on the substrate covering the apertures, reflowing the dielectric film to flow into the apertures and to form a dielectric film adherent to the substrate, to provide a continuous dielectric extending from the dielectric film into the apertures. In certain embodiments, after filling, additional apertures, such as vias, are photoimaged in the dielectric film. Preferably the vias are then metallized, and circuitry formed atop the dielectric film.Type: GrantFiled: September 24, 1998Date of Patent: March 20, 2001Assignee: International Business Machines CorporationInventors: John M. Lauffer, Voya R. Markovich, Cheryl L. Palomaki, William E. Wilson
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Patent number: 6195883Abstract: A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.Type: GrantFiled: March 25, 1998Date of Patent: March 6, 2001Assignee: International Business Machines CorporationInventors: Anilkumar C. Bhatt, Voya R. Markovich, Irving Memis, William E. Wilson