Abstract: The present invention is directed to, among other things, processes for purifying polyether polyols via treatment with an ion exchange resin in which the ion exchange resin is disposed in a container that is operated liquid-full.

Abstract: This invention relates to a process for preparing a stable low viscosity polymer polyol having a solids content of at least about 30% by weight. This process comprise free-radically polymerizing one or more base polyols, one or more pre-formed stabilizers, and one or more ethylenically unsaturated monomers in the presence of one or more free-radical polymerization initiators, and one or more polymer control agents; in which the process is restarted after being stopped by (I) restarting the feed of base polyol and the initiator; (II) continuing the base polyol and initiator feed until the total feed amounts to at least 5% of the total reactor volume; and (III) restarting the feed of the ethylenically unsaturated monomers in which the ratio of monomers to total feed is ramped up to its final value over a period of not less than 25% of the reactor residence time. This process is particularly suitable for restarting the process of production after any planned or unplanned reactor shutdown.

Abstract: This invention relates to a process for preparing a stable low viscosity polymer polyol having a solids content of at least about 30% by weight. This process is particularly suitable for restarting the process of production after any reactor shutdown (planned or unplanned).

Abstract: A toilet assembly is provided having a bowl assembly having an inlet, a wastewater outlet, and a water supply inlet having an inlet valve. The assembly includes an adjustable metering valve in fluid communication with the inlet valve and the inlet of the bowl assembly, and an accumulator in fluid communication with the inlet valve and disposed upstream of the adjustable metering valve. A fragmentation passage is provided in fluid communication with the wastewater outlet and disposed downstream of the wastewater outlet. The assembly includes jet assembly having an inlet in fluid communication with the inlet valve, and an outlet disposed upstream of the fragmentation passage. The water supply inlet is structured to deliver a quantity of water through the inlet of the bowl assembly, and a quantity of water to the jet assembly to remove wastewater from the fragmentation passage.

Abstract: A toilet assembly is provided having a bowl assembly having an inlet, a wastewater outlet, and a water supply inlet having an inlet valve. The assembly includes an adjustable metering valve in fluid communication with the inlet valve and the inlet of the bowl assembly, and an accumulator in fluid communication with the inlet valve and disposed upstream of the adjustable metering valve. A fragmentation passage is provided in fluid communication with the wastewater outlet and disposed downstream of the wastewater outlet. The assembly includes jet assembly having an inlet in fluid communication with the inlet valve, and an outlet disposed upstream of the fragmentation passage. The water supply inlet is structured to deliver a quantity of water through the inlet of the bowl assembly, and a quantity of water to the jet assembly to remove wastewater from the fragmentation passage.

Abstract: An emulator executes on a second data processing system as a second system user level process including a first system user level program, a first system executive program, and first system user and executive tasks. An emulator level is interposed between the second system user level process and a kernel level and contains pseudo device drivers. Each pseudo device driver corresponds to a first system input/output device. The kernel level includes kernel processes, each kernel process corresponding to a pseudo device driver. The second system hardware platform includes a plurality of second system input/output devices, wherein each second system input output device corresponds to a kernel process. Each combination of a pseudo device driver, a corresponding kernel process and a corresponding second system input/output device executes in a second system process and emulates the operations of a corresponding first system input/output task and the corresponding first system input/output device.

Abstract: An application such as an interpretative emulator executes a wide range of different classes of emulated program instructions developed for the processor architecture being emulated on a host system which includes an dual integer pipelined execution unit. The sets of RISC instructions which execute emulated program instructions are organized within the emulator so as to be processed as two distinct instruction streams by the dual integer pipelined execution units wherein one of the pipelined unit performs the steps necessary to completing a current or foreground like operation on each emulated program instruction while the other pipelined unit performs the steps of an anticipated lookahead or background like operation on the next emulated program instruction.

Abstract: A memory translation mechanism and method executing in a second system to perform first system memory operations for first system executive and user tasks executing on the second system which includes a second system memory organized as a plurality of memory segments, wherein first memory segments are designated to correspond to system memory areas and second memory segments are designated to correspond to user memory areas, and wherein each memory segment corresponds to a combination of a type of first system task and a type of a first system memory area. An interpreter maps by reading an identification of the type of the task corresponding to the first system virtual address from the task type memory and the area type value from the first system virtual address and determining a memory segment corresponding to the type of the first system task and the type of first system area referenced by the first system virtual address.

Abstract: An assembly for use by a surveyor having a ruler and an apparatus for securing the ruler to a surveyor's pole. The ruler has a retractable tape and a belt clip. The apparatus for securing the ruler to a pole includes a cradle sized to retain the ruler, a stop member, a planar wall member and attachment members for securing the apparatus to a pole. By securing the ruler to a pole, a single person may complete measurements which previously required two people. The tape of the ruler includes measurements which are inverted with respect to the tenth of a foot for easier reading.

Abstract: A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.

Abstract: A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.

Abstract: A method and apparatus pertaining to a firmware control unit for detecting when such control unit is not behaving properly. The control unit is organized to include in each location of the unit's control store, to which control is not expected to transfer, a predetermined type of pattern containing an address specifying the address of that location, a suitable tag identifying the probable reason for the unexplained jump, and a transfer of control to the appropriate entry point in a reporting firmware routine within the control store. The reporting firmware routine has a number of entry points for collecting all the executions of unexpected locations and for storing the appropriate address and tag information in a predetermined register file for later referencing by an unusual event (UEV) handler routine.

Abstract: Disclosed is an apparatus for diluting and dispensing fluid concentrates which comprises a frame having a least one compartment therein for insertion of a liquid holding container. Mounted within the frame is a water valve housing which is adapted to interface with a venturi housing affixed to the liquid holding container. The water valve housing has affixed thereto a valve which is manually actuated. In response to the depression or release of the actuation means, the valve is substantially either fully open or fully closed. The water valve housing includes locking means for preventing the valve from being operated by the manual actuation means when the liquid holding container is not properly inserted into the dilution station. The refill modules of the present invention include the venturi housing and liquid holding container mentioned above.

Abstract: A last-in, first-out register having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the addresses already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be retransferred to the buffer address register for read out.

Abstract: A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

Abstract: A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded.

Abstract: A data selection matrix is disclosed which uses a plurality of programmed array logic (PAL) units having input thereto portions of binary words from a plurality of sources, the PALs being responsive to control words also input thereto to jointly select one of said sources of binary words and to select the arrangement of the portions of the binary words being input thereto from the selected source of binary words.

Abstract: An address boundary detector is disclosed that functions with an arithmetic logic unit (ALU) in a computer processor while the ALU generates addresses by adding an offset or displacement to a base address. The detector monitors bits of addresses to determine whether a data item can be completely stored within the same block or page of memory as that addressed by the base address from which it was derived.

Abstract: A multifunction arithmetic indicator that is associated with and controlled by an arithmetic logic unit (ALU) to store standard arithmetic indicator information such as overflow, carry, arithmetic sign and all bits equal zero that are generated by the ALU when processing binary information. A control unit sends control signals to multiplexers in the multifunction arithmetic indicator that cause the selection of appropriate arithmetic indicator information from the ALU, no matter what the bit length of binary words being processed by the ALU. The selected indicator information is stored in a register for later use.

Abstract: A binary arithmetic unit performs arithmetic operations on binary coded decimal (BCD) operands by converting the BCD digits to hexadecimal excess 3 digits, generating hexadecimal excess 6 partial product digits and modifying selected excess 6 partial product digits to generate a BCD result.