Abstract: What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement.

Abstract: A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

Abstract: The invention is a weld metal for welding of a titanium alloy member to a ferrous based alloy member as an intermediate transition zone between such members so as to overcome the metallurgical imcompatability of each such member, and which consists of a vanadium metal, titanium and iron and inconsequential amounts of brittle intermetallic compounds. The preferred weld metal is vanadium rich and contains no more than 50% combined weight of titanium and such a weld metal is produced in accordance with our invention by fusion welding, particularly capacitor discharge welding, which because of its inherent but heretofore unrecognized extremely fast quench or freeze rates will produce a fusion weld between these two metallurgically incompatible alloys which is free of brittle intermetallic compounds. It is also part of our invention that such a weld metal of the aforesaid composition will have independent use as a welding alloy, particularly when fabricated in sheet form.

Abstract: A priority resolver for providing unambiguous resolution of requests among competing processes vying for access to a common device and which is adapted to a non-distributed environment.

Abstract: A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.

Abstract: A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

Abstract: This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.

Abstract: A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.

Abstract: A delivery device and method making use of a plunger which can be controllable reciprocated within a housing to regulate the amount of material expelled from the housing. The plunger includes an adjustable stop collar which can be adjustably positioned, preferably by depressing the sides of the collar. In addition, a piston within the housing is sealably releasable from the plunger.

Abstract: A liquid containing a contaminant such as water or polymeric solids is purified. Purification of a liquid containing a contaminant is enhanced by the use of second fractionating column in conjunction with a first fractionating column to recover a portion of the liquid to be purified from the kettle product of the first column. Vapor from a second fractionating column is used to control the total energy input to a first fractionating column.

Abstract: Use of a control storage device coupled with a central processing unit is locked, during the loading process from the unit to the device, to a would-be user of the device until such loading process is complete as indicated by a so-called "unlock" command received from the central processing unit. An indication of an error or malfunction in the control storage device either during the loading process or thereafter is also provided to the central processing unit.

Abstract: A method for electroslag welding of railroad rails under field conditions employs a special mold bottom member and a special guide tube structure. The mold bottom member includes a metallic insert which is supported by heat-insulating means, e.g. ceramic material in a cavity in a bottom copper block. The ceramic effectively heat insulates the insert from the copper block so when arcing takes place at the start of the welding, the heat is retained by the insert, which forms part of the weld. The guide tube structure is flared toward the bottom and guides two continuously fed electrodes. The structure includes wing-like members near its bottom end. The bottom of the structure is designed wth sharp corners, so that when arcing takes place some of the guide structure metal melts to form a uniform layer of molten metal, which aids in the melting of flux into a slug bath of uniformly distributed temperature.

Abstract: A novel process for the purification of used oil comprising removing the ash-forming components, then subjecting the oil to vacuum fractionation. A novel vacuum fractionation column is also disclosed.

Abstract: A novel process for the purification of used oil comprising removing the ash-forming components, then subjecting the oil to vacuum fractionation. A novel vacuum fractionation column is also disclosed.

Abstract: In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.

Abstract: In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit.

Abstract: A harnessing device formed by a locking head and an attached webbed strap. The head contains oppositely positioned locking tangs in a guide channel that receives the strap after encirclement of items to be harnessed. The tangs engage abutments of the webbed strap for adjustable retention of the harnessed items. The strap is advantageously molded of a stretch reorientable material. Stretching produces a relatively thin and strengthened web which resists penetration by the locking tangs and reduces the possibility of failure by fracture or reverse rotation. The inclusion of the relatively thin web also promotes homogeneity during molding and avoids imperfections that can cause failure in other types of straps.