Patents by Inventor William F. Bruckert

William F. Bruckert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8799706
    Abstract: A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: August 5, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: William F. Bruckert, David J. Garcia, Thomas A. Heynemann, James S. Klecka, Jeffrey A. Sprouse
  • Patent number: 8103861
    Abstract: A method and system of presenting an interrupt request to processors executing in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor configured to execute a program, a second processor configured to execute a duplicate copy of the program in lock step with the first processor, and a logic device coupled to the processors. The logic device is configured to present an interrupt request to the processors when the processors are at substantially the same computational point in the program.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: January 24, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James S. Klecka, William F. Bruckert, Mihai Damian, Peter A. Reynolds, Dale E. Southgate
  • Patent number: 7933966
    Abstract: A method and system of copying a memory area between processor elements for lock-step execution. At least some of the illustrative embodiments may be a method comprising executing duplicate copies of a first program in a first processor of a first multiprocessor computer system and in a first processor of a second multiprocessor computer system (the executing substantially in lock-step), executing a second program in a second processor element of the first multiprocessor computer system (the first and second processors of the first multiprocessor computer system sharing an input/output (I/O) bridge), copying a memory area of the second program executing in the second processor element of the first multiprocessor computer system to a memory of a second processor element in the second multiprocessor computer system while the duplicate copies of the first program are executing in the first processor elements, and then executing duplicate copies of the second program in the second processors in lock-step.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: April 26, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thomas J. Kondo, Robert L. Jardine, James S. Klecka, William F. Bruckert, David J. Garcia, James R. Smullen, Patrick H. Barnes
  • Patent number: 7730350
    Abstract: A method and system of determining the execution point of programs executed in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor that executes a program, and a second processor that executes a duplicate copy of the program in lock step with the first processor. After receipt of a duplicate copy of an interrupt request by each processor, the first processor determines the execution point in its program relative to the execution point of the duplicate copy of the program executed by the second processor.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: June 1, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dale E. Southgate, Mihai Damian, Peter A. Reynolds, William F. Bruckert, James S. Klecka
  • Patent number: 7590885
    Abstract: A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing to execute a duplicate copy of the user program on a source processor (the source processor coupled to a second memory and generating writes to the second memory), duplicating memory writes of the source processor and duplicating writes by input/output adapters to create a stream of duplicate memory writes, and applying the duplicated memory writes to the first memory.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: September 15, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thomas J. Kondo, Robert L Jardine, William F. Bruckert, David J. Garcia, James S. Klecka, James R. Smullen, Jeff Sprouse, Graham B. Stott
  • Patent number: 7549082
    Abstract: A method and system of bringing processors to the same computational point. At least some of the illustrative embodiments are computer systems comprising a first processor executing a program, a second processor executing a duplicate copy of the program (but at different computational points in the program), and a shared main memory coupled to the first and second processors. When the processors each receive duplicate copies of an interrupt request, the processors are configured to bring their respective programs to the same computational points prior to servicing the interrupt request.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: June 16, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dale E. Southgate, Mihai Damian, Peter A. Reynolds, William F. Bruckert, James S. Klecka
  • Patent number: 7516358
    Abstract: A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors, and adjusting the core voltages of the plural processors within the operating range to tune the plural processors.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: April 7, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Juerg Haefliger, William F. Bruckert, James S. Klecka
  • Patent number: 7434098
    Abstract: Method and system of determining whether a user program has made a system level call and thus whether the user program is uncooperative with fault tolerant operation. Some exemplary embodiments may be a processor-based method comprising providing information from a first processor to a second processor (the information indicating that a user program executed on the first processor has not made a system level call in a predetermined amount of time), and determining by the first processor, using information from the second processor, whether a duplicate copy of the user program substantially simultaneously executed in the second processor has made a system level call in the predetermined amount of time.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: October 7, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David L. Bernick, William F. Bruckert, David J. Garcia, Robert L. Jardine, Pankaj Mehra, James R. Smullen
  • Patent number: 7426656
    Abstract: A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: September 16, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David L. Bernick, William F. Bruckert, David J. Garcia, Robert L. Jardine, James S. Klecka, Pankaj Mehra, James R. Smullen
  • Patent number: 7426614
    Abstract: A method and system of executing duplicate copies of a program in lock step. Some illustrative embodiments are a computer system comprising a first processor executing a program, a second processor executing a duplicate copy of the program (the first processor and second processor executing their respective programs in lock step), a logic device coupled to the processors, and a shared device coupled to the processors through the logic device. The first processor presents to the logic device a first operation involving the shared device, and the second processor does not present an operation, or presents an operation that does not match the first operation. The logic device obtains a second operation from the second processor that matches the first operation, and wherein a single operation that matches the first and second operations is presented to the shared device.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: September 16, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: William F. Bruckert, Mihai Damian, James S. Klecka, Peter A. Reynolds, Dale E. Southgate
  • Publication number: 20070282967
    Abstract: A method and system of implementing a persistent memory. At least some of the illustrative embodiments are a system comprising a first computer slice comprising a memory, a second computer slice comprising a memory (the second computer slice coupled to the first computer slice by way of a communication network at least partially external to each computer slice), and a persistent memory comprising at least a portion of the memory of each computer slice (the portion of the memory of the first computer slice storing a duplicate copy of data stored in the portion of the memory of the second computer slice). The persistent memory is accessible to an application program through the communication network.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 6, 2007
    Inventors: Samuel A. Fineberg, Pankaj Mehra, David J. Garcia, William F. Bruckert
  • Patent number: 6950428
    Abstract: Adaptive sets of lanes are configured between routers in a system area network. Source nodes determine whether packets may be adaptively routed between the lanes by encoding adaptive control bits in the packet header. The adaptive control bits also facilitate the flushing of all lanes of the adaptive set. Adaptive sets may also be used in uplinks between levels of a fat tree.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: September 27, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert W. Horst, William J. Watson, David A. Brown, David J. Garcia, William P. Bunton, David T. Heron, William F. Bruckert
  • Patent number: 6393582
    Abstract: A logical processor is formed from a pair of processor units operating in close synchrony to perform self-check operations. Outputs of one of the processor units are compared to that of the other processor unit. When one of the processor units experiences an error, creating a divergence, that error and/or divergence will be made known to the Master processor which will then determine if recovery from the error can be made and, if so, save its processing state to memory, cause a reset of both processor units to an initial state to begin executing reinitialization code using the prior saved state for both processor units.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: May 21, 2002
    Assignee: Compaq Computer Corporation
    Inventors: James Stevens Klecka, William F. Bruckert, Robert L. Jardine
  • Patent number: 6233702
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 15, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Robert W. Horst, David J. Garcia, William Patterson Bunton, William F. Bruckert, Daniel L. Fowler, Curtis Willard Jones, Jr., David Paul Sonnier, William Joel Watson, Frank A. Williams
  • Patent number: 5751932
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 12, 1998
    Assignee: Tandem Computers Incorporated
    Inventors: Robert W. Horst, William Edward Baker, Randall G. Banton, John Michael Brown, William F. Bruckert, William Patterson Bunton, Gary F. Campbell, John Deane Coddington, Richard W. Cutts, Jr., Barry Lee Drexler, Harry Frank Elrod, Daniel L. Fowler, David J. Garcia, Paul N. Hintikka, Geoffrey I. Iswandhi, Douglas Eugene Jewett, Curtis Willard Jones, Jr., James Stevens Klecka, John C. Krause, Stephen G. Low, Susan Stone Meredith, Steven C. Meyers, David P. Sonnier, William Joel Watson, Patricia L. Whiteside, Frank A. Williams, Linda Ellen Zalzala
  • Patent number: 5689689
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 18, 1997
    Assignee: Tandem Computers Incorporated
    Inventors: Steven C. Meyers, John Michael Brown, William F. Bruckert, James Stephens Klecka
  • Patent number: 5675579
    Abstract: A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 7, 1997
    Assignee: Tandem Computers Incorporated
    Inventors: William Joel Watson, William Edward Baker, William F. Bruckert, William Patterson Bunton, David J. Garcia, Robert W. Horst, Geoffrey I. Iswandhi, David Joseph Kinkade, David Paul Sonnier
  • Patent number: 5291494
    Abstract: The software error handling determines the nature of the fault and takes different action depending upon the nature of the fault. If the fault prevents the data processing system from continued reliable operation, then the element causing the fault is immediately disabled. Otherwise, the element which is the source of the fault is treated so that it does no harm to the system and causes no further faults. The element can then be completely handled during normal software status checks.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: March 1, 1994
    Assignee: Digital Equipment Corporation
    Inventors: William F. Bruckert, Thomas D. Bissett, James Melvin
  • Patent number: 5255367
    Abstract: A dual processor computer system includes a first processing system having a central processing unit which executes a series of data processing instructions, a data bus system for transferring data to and from the first central processing unit, a memory unit coupled to the first central processing unit, and a cross-link communications element for transferring data into and out of the first processing system. A similarly configured second processing system, operating independently of the first processing system, is also provided. The cross-link communications element associated with the second processing system is coupled to the cross-link communication element of the first processing system, for transferring data into the second processing system from the first processing system and for transferring data into the first processing system from the second computer system.
    Type: Grant
    Filed: July 19, 1989
    Date of Patent: October 19, 1993
    Assignee: Digital Equipment Corporation
    Inventors: William F. Bruckert, Thomas D. Bissett, Dennis Mazur, John Munzer
  • Patent number: 5249187
    Abstract: A dual processor data processing system having interprocessor error checking includes a first central processing unit executing a series of instructions. A second central processing unit executes the same series of instructions independently of and in synchronism with the first central processing unit. A first data bus is coupled to the first central processing unit for receiving data to be input to the first central processing unit and a second data bus is coupled to the second central processing unit for receiving data to be input to the second central processing unit. Error checking devices are coupled to the first and second data busses for checking data transmitted over the first and second data busses and for detecting errors on I/O reads prior to delivery of the data to the first and second central processing units. The error checking devices include comparison means for indicating an error when the data on the first and second data busses are unequal.
    Type: Grant
    Filed: May 25, 1989
    Date of Patent: September 28, 1993
    Assignee: Digital Equipment Corporation
    Inventors: William F. Bruckert, Thomas D. Bissett