Abstract: Hardware error processing is undertaken to analyze the source of the error and to preserve sufficient information to allow later software error processing. The hardware error processing also allows, for certain errors, complete recovery without interruption of the sequence of instruction execution.

Abstract: A fault tolerant computer system has a central processing system which includes at least one set of data pathways, and executes a series of data processing instructions including the transfer of messages along the plurality of data pathways. At least one set of transaction data storage devices are coupled to the data pathways for storing a predetermined number of successive messages transferred most recently on the data pathways. Error checking devices are included for detecting the presence of errors in the central processing system. Error storage devices are coupled to the transaction data storage devices and the error checking devices for causing the transaction data storage devices to cease storing additional messages in response to the detection of errors by the error checking device.

Abstract: A data handling system for transferring data between two units, the data being transferred in blocks of a selected number of data words, up to predetermined maximum number. A buffer stores the data being transferred. The buffer includes a plurality of stages arranged serially from an input end to an output end, the number of stages being equal in number to the predetermined maximum number of data words that may be transferred in a block. If the number of data words being transferred is less than the predetermined maximum number, as indicated by a control signal from the unit transmitting the data, the buffer either receives the data in the stage a number of stages from the output end, or transmits the data from the stage a number of stages from the input end, equal to the number of words being transferred in the block.

Abstract: A fault tolerant computer system having a first processing system which includes a first data processor for executing a series of data processing instructions. A first data output terminal outputs data from the first processing system. A second processing system, substantially identical to the first processing system, operates independently from the first processing system. The second processing system includes a second data processor for executing the series of data processing instructions in the same sequence as the first data processor. It also includes a second data output terminal for outputting data from the second processing system. A synchronizing device is coupled to the first and second data processors for maintaining the execution of the series of data processing instructions by the first and second processing systems in synchronism.

Abstract: A fault tolerant computer system includes a fault tolerant data processing module which has means for detecting and correcting errors in the operation of the data processing module to maintain a high degree of data integrity. Data transmission control devices control the transmission of all data to the fault tolerant data processing module and the receipt of all data into the fault tolerant data processing module. Input/output terminals are coupled to the data transmission control means for receiving and transmitting data. A non-fault tolerant input/output module is coupled to transmit the data to the input/output terminals of the fault tolerant data processing module. This module includes a read device for transferring data to the fault tolerant computing system in response to requests from the data transmission control devices, and a firewall for preventing the non-fault tolerant input/output module from initiating transfers of data to the fault tolerant data processing module.

Abstract: A dual processor computer system with error checking includes a first processing system for executing a series of instructions including output instructions. A second processing system executes the series of instructions independently of and in synchronism with the first processing system. Shared resource devices are coupled to the first and second processing systems for receiving data from output instructions from the first and second processing systems substantially simultaneously. Error checking devices are located downstream of the shared resource means for checking the data received from the first and second processing systems only following a write operation into the shared resource means.

Abstract: A dual processor data processing system having interprocessor error checking includes a first central processing unit executing a series of instructions. A second central processing unit executes the same series of instructions independently of and in synchronism with the first central processing unit. A first data bus is coupled to the first central processing unit for receiving data to be input to the first central processing unit and a second data bus is coupled to the second central processing unit for receiving data to be input to the second central processing unit. Error checking devices are coupled to the first and second data busses for checking data transmitted over the first and second data busses and for detecting errors on I/O reads prior to delivery of the data to the first and second central processing units. The error checking devices include comparison means for indicating an error when the data on the first and second data busses are unequal.

Abstract: A data transfer system for use in transferring data between a memory and an input/output system in a digital data processing system. The data transfer system includes a plurality of buffers into which data can be loaded from the memory or the input/output system. A buffer control selects the buffer to be loaded, and control signals from the memory govern the transfer of data from the memory into and out of the selected buffer.

Abstract: A central processor unit for a digital data processing system that processes prefetched instructions including a conditional branch instruction. The processor includes a fetch unit that has separate portions, one that retrieves operands and the other that retrieves instructions. When the fetch unit fetches a conditional branch instruction, it may continue to prefetch "branch not taken" instructions using the instruction fetch portion. The fetch unit initially uses the operand fetch portion to prefetch "branch taken" instructions. If it is determined that the branch is not taken, the prefetch operation is aborted, otherwise the prefetch operation is allowed to continue to provide the next instruction used by the processor.

Abstract: A memory for use in a digital data processing system, the memory including a memory controller and one or more memory arrays. A memory array performs refresh operations transparently to the memory controller, but in synchronization with a system timing signal while it is receiving normal system power. A memory array also includes asynchronous refresh circuitry for controlling refresh while the system power is interrupted and the array receives no system timing signal. When each refresh operation occurs during power interruption, the asynchronous refresh circuitry tests the condition of the system power supply. Since refresh operations are transparent to the memory controller, the memory array indicates when the memory operations are completed. If the memory operation is a read operation, the memory controller then controls the transfer of data from the array to the controller.

Abstract: In a data processing system, a memory (32) consists of data words and associated error-correction codes that are independently accessible; it is possible simultaneously to read a data word and write its associated error-correction code. This allows a memory-control circuit (30) immediately to store in the memory (32) a data word sent by a processor (10) while it is concurrently in the process of generating the error-correction code for that data word. The result is that the memory-control circuit (30) can subsequently fetch the newly stored data word before storage of its associated error-correction code is complete. This reduces delays involved in error-correction-code generation. The data word includes not only non-redundant information but also parity bits that both the processor (10) and the memory-control circuit (30) employ to determine whether a data word is correct.