Abstract: A system and method is disclosed for a distributed out-of-band (OOB) management controller system enabling efficient usage of power while providing multiple methods and levels of communication between intelligent devices. Two or more management controllers collaboratively operate in a predetermined manner including, but not limited to, peer-to-peer, master/slave, or independently. Management information consistency is maintained across a system's power states by implementing distributed intelligent devices that directly interact as communication devices to local or remote management consoles. A management protocol is implemented such that management information is communicated between managed elements and management controllers over physical interfaces or via a network connection.

Abstract: Audio and visual information processing components are co-located on a PCI Express graphics card by communicating audio and visual information received through the PCI Express interface of the graphics card to a PCI Express switch which switches audio information to audio processing components and video information to video processing components for processing of the information to an audiovisual appliance output. The audio processing components may include an AC97 interface and CODEC or an audio controller that processes PCI Express information. The audiovisual output signal may include a variety of combined or separate audiovisual appliance compatible outputs such as coaxial cable output, EVC output, HDMI output, HDTV output or 1394 output.

Abstract: A system and method for securing access to memory modules includes a memory module, a virtual memory module, a boot module, and a gatekeeper. The boot module accepts a key and requests for the memory module and provides the requests and the key to the virtual memory module. The virtual memory module is externally accessible by the boot module and accepts the provided key and the requests from the boot module and transmits the requests and the provided key from the boot module to the gatekeeper. The gatekeeper regulates access to the memory module allowing no other components to directly access the memory module. The gatekeeper receives the provided key from the virtual memory module and the gatekeeper authenticates the provided key by comparing it with a stored key stored in secure location. Upon proper authentication of the provided key, the gatekeeper executes the request in the memory module.

Abstract: An information handling system includes support for dynamic power throttling. In one embodiment, an information handling system includes power level detection and power control modules. The power level detection module may monitor power consumption for the information handling system and may automatically transmit power level data to a power level manager, based on the monitored power consumption. The power control module may receive power control data from the power level manager. The power control module may also automatically adjust power consumption of the information handling system, in accordance with the power control data received from the power level manager. In another embodiment, an information handling system may include an interface and a power level manager. The power level manager may receive power information for computers via the interface, may automatically compute an adjusted power threshold setting, and may automatically transmit the adjusted power threshold setting to a computer.

Abstract: A system and method for using a switch to route graphics data and data for a peripheral data on an interconnect is disclosed. A graphics card includes a switch that is communicatively coupled to a computer system. The switch receives graphics data and data for a peripheral device from the computer system via a first link. The switch routes the data for a peripheral device to a console via a second link and routes the graphics data to a graphics controller via a third link. The graphics controller forms a part of the graphics card and is communicatively coupled to the switch via the third link, wherein the graphics controller generates a video signal to drive a video display.

Abstract: Apparatus provides a method and system for interfacing expansion cards having different device types to a standard connector. In this manner, the number of different types of connectors in an information handling system is reduced. One embodiment includes a direct path between the card connector and a first bus if the type of device on the expansion card is compatible with the first bus. If the type of device on the expansion card is not compatible with the first bus, then a translation path is provided between the card connector and the first bus. The translation path may include one or more integrated functions that can be selected by the expansion card according to their needs.

Abstract: A universal bus communicates information by one of plural bus protocols. A bus protocol selector is operable to select one of the plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol. An Input/Output chip includes a protocol selector unit that selects a bus protocol I/O unit to communicate with the device over the universal bus. The bus protocol I/O unit communicates over the universal bus by using a bus protocol that is compatible with the device. For instance, the one of plural available differential serial bus protocols is selected so that the bus protocol I/O unit communicates with the device using a bus protocol compatible with the device. In some instances, a bypass circuit configures the physical characteristics of the universal bus, such as by interfacing or removing a capacitor with the universal bus to support AC or DC coupled bus protocols.

Abstract: A universal bus communicates information by one of plural bus protocols. A bus protocol selector is operable to select one of the plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol. An Input/Output chip includes a protocol selector unit that selects a bus protocol I/O unit to communicate with the device over the universal bus. The bus protocol I/O unit communicates over the universal bus by using a bus protocol that is compatible with the device. For instance, the one of plural available differential serial bus protocols is selected so that the bus protocol I/O unit communicates with the device using a bus protocol compatible with the device. In some instances, a bypass circuit configures the physical characteristics of the universal bus, such as by interfacing or removing a capacitor with the universal bus to support AC or DC coupled bus protocols.

Abstract: A system and method for using a switch to route graphics data and data for a peripheral data on an interconnect is disclosed. A graphics card includes a switch that is communicatively coupled to a computer system. The switch receives graphics data and data for a peripheral device from the computer system via a first link. The switch routes the data for a peripheral device to a console via a second link and routes the graphics data to a graphics controller via a third link. The graphics controller forms a part of the graphics card and is communicatively coupled to the switch via the third link, wherein the graphics controller generates a video signal to drive a video display.

Abstract: A system and method for using a switch to route graphics data and data for a peripheral data on an interconnect is disclosed. A graphics card includes a switch that is communicatively coupled to a computer system. The switch receives graphics data and data for a peripheral device from the computer system via a first link. The switch routes the data for a peripheral device to a console via a second link and routes the graphics data to a graphics controller via a third link. The graphics controller forms a part of the graphics card and is communicatively coupled to the switch via the third link, wherein the graphics controller generates a video signal to drive a video display.

Abstract: A universal bus communicates information by one of plural bus protocols. A bus protocol selector is operable to select one of the plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol. An Input/Output chip includes a protocol selector unit that selects a bus protocol I/O unit to communicate with the device over the universal bus. The bus protocol I/O unit communicates over the universal bus by using a bus protocol that is compatible with the device. For instance, the one of plural available differential serial bus protocols is selected so that the bus protocol I/O unit communicates with the device using a bus protocol compatible with the device. In some instances, a bypass circuit configures the physical characteristics of the universal bus, such as by interfacing or removing a capacitor with the universal bus to support AC or DC coupled bus protocols.

Abstract: A universal bus communicates information by one of plural bus protocols. A bus protocol selector is operable to select one of the plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol. An Input/Output chip includes a protocol selector unit that selects a bus protocol I/O unit to communicate with the device over the universal bus. The bus protocol I/O unit communicates over the universal bus by using a bus protocol that is compatible with the device. For instance, the one of plural available differential serial bus protocols is selected so that the bus protocol I/O unit communicates with the device using a bus protocol compatible with the device. In some instances, a bypass circuit configures the physical characteristics of the universal bus, such as by interfacing or removing a capacitor with the universal bus to support AC or DC coupled bus protocols.

Abstract: A method of performing a remote diagnostic test on an information handling system that is connected to a network and is responsive to test mode packets is disclosed. The method includes transmitting a test mode packet to the information handling system via a network, transmitting a test command packet to the information handling system via the network; and receiving a test result via the network. Additionally, the method includes receiving a test mode packet via a network, where the test mode packet is configured to place a device of the information handling system in an operational state, receiving a test command packet via the network, where the test command packet causing a test to be performed on the information handling system, and transmitting the test results of the test via the network.

Abstract: A single group of signals interfaces a computer system to either an analog display or a digital display. A video signal in digital format and a video signal in analog format are both supplied to a circuit that multiplexes the digital signal and the analog signal, generating an appropriate output signal for the display, either analog or digital, that is coupled to the computer system. In one example, the signal connector interfaces the computer system to either an analog CRT display or a digital FPD display. The multiplexer multiplexes the analog signal and the digital signal supplied by the computer system and generates an output signal that is suitable for the CRT display or the FPD display, depending on the type of display coupled to the computer system.

Abstract: A multiprocessor which includes a plurality of processing units interconnected by a global bus. Each processing unit has the capability for initiating control instructions including notification instructions and for selectively transmitting the control instructions over the global bus to the plurality of processing units and trigger device for initiating execution of the control instructions as a destination processing unit. A multiprocessor so constructed is capable of executing blocks of instructions sequentially or concurrently or both at required by a single program to reduce program execution time to a minimum.