Patents by Inventor William G. America

William G. America has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8106485
    Abstract: A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: William G. America, Steven H. Johnston, Brian W. Messenger
  • Publication number: 20080224273
    Abstract: A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 18, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William G. AMERICA, Steven H. Johnston, Brian W. Messenger
  • Patent number: 7368393
    Abstract: A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure comprising a dual damascene structure that has been treated by the method is disclosed.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: May 6, 2008
    Assignee: International Business Machines Corporation
    Inventors: William G. America, Steven H. Johnston, Brian W. Messenger
  • Patent number: 7129159
    Abstract: A dual damascene conductor structure is formed on a substrate with an exposed conductor on top covered by a buried cap, a dielectric layer (DL) and an organic layer (OL). Form a lower via hard mask layers over the OL and form a top trench patterning hard mask over the lower, via hard mask. Form a trench pattern hole through the trench hard mask layer; and form a via pattern hole through the via hard mask layer in a region exposed below the trench pattern hole. Etch a via pattern hole into the OL and then etch a via pattern hole down into the DL. Etch away the trench pattern layer and the OL layer below the trench pattern hole. Etch the via hole through the DL exposing the cap while simultaneously partially etching the DL to a final trench depth to form a trench in the DL below the trench pattern hole, with the trench having a bottom above the cap and sidewalls in the DL.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: William G. America, Steven H. Johnston
  • Patent number: 7091164
    Abstract: A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: August 15, 2006
    Assignees: Eastman Kodak Company, Ferro Corporation, Clarkson University
    Inventors: Ramanathan Srinivasan, Suryadevara V. Babu, William G. America, Yie-Shein Her
  • Patent number: 6875688
    Abstract: A method for implementing dual damascene processing includes forming a first hardmask layer over an interlevel dielectric layer, and forming a second hardmask layer over the first hardmask layer. A trench pattern is opened within a third hardmask layer formed over the second hardmask. A first etch process is implemented so as to define a via pattern completely through the second hardmask layer and partially through the first hardmask layer, and a second etch process is implemented to transfer the trench pattern and the via pattern into the interlevel dielectric layer.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: April 5, 2005
    Assignee: International Business Machines Corporation
    Inventors: William G. America, Kaushik A. Kumar
  • Publication number: 20040175934
    Abstract: A method for forming an interconnect structure in a semiconductor device includes defining a first insulator layer on a substrate and defining a via in the first insulator layer, thereby exposing a portion of the substrate. A sacrificial material is deposited over the first insulator layer and within the via, the sacrificial material being deposited at a thickness so as to also form a second insulator layer. A metallization line trench is defined in the second insulator layer, the trench being aligned over the via. Then, the sacrificial material is removed from the via opening, thereby allowing the via and the trench to be filled with a conductive material by dual damascene processing, wherein the formation of the trench and the removal of the sacrificial material from the via is implemented through a single etching operation.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 9, 2004
    Applicant: International Business Machines Corporation
    Inventors: William G. America, Parijat Bhatnagar, Eugene J. O'Sullivan, Richard S. Wise
  • Publication number: 20040051077
    Abstract: A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.
    Type: Application
    Filed: July 11, 2003
    Publication date: March 18, 2004
    Inventors: Ramanathan Srinivasan, Suryadevara V. Babu, William G. America, Yie-Shein Her
  • Patent number: 6627107
    Abstract: A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: September 30, 2003
    Assignee: Eastman Kodak Company
    Inventors: Ramanathan Srinivasan, Suryadevara V. Babu, William G. America, Yie-Shein Her
  • Patent number: 6544892
    Abstract: The present invention relates to an aqueous slurry that is particularly useful for removing silicon dioxide in preference to silicon nitride by chemical-mechanical processing. The aqueous slurry according to the invention includes abrasive particles and an organic compound having both a carboxylic acid functional group and a second functional group selected from amines and halides. The present invention also relates to a method of removing silicon dioxide in preference to silicon nitride from a surface of an article by chemical-mechanical polishing. The method includes polishing the surface using a polishing pad, water, abrasive particles, and an organic compound having both a carboxylic acid functional group and a second functional group selected from amines and halides. The abrasive particles can be dispersed in the aqueous medium or they can be bonded to the polishing pad.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: April 8, 2003
    Assignee: Eastman Kodak Company
    Inventors: Ramanathan Srinivasan, Suryadevara V. Babu, William G. America, Yie-Shein Her
  • Publication number: 20030006397
    Abstract: A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 9, 2003
    Inventors: Ramanathan Srinivasan, Suryadevara V. Babu, William G. America, Yie-Shein Her
  • Publication number: 20020195421
    Abstract: The present invention relates to an aqueous slurry that is particularly useful for removing silicon dioxide in preference to silicon nitride by chemical-mechanical processing. The aqueous slurry according to the invention includes abrasive particles and an organic compound having both a carboxylic acid functional group and a second functional group selected from amines and halides. The present invention also relates to a method of removing silicon dioxide in preference to silicon nitride from a surface of an article by chemical-mechanical polishing. The method includes polishing the surface using a polishing pad, water, abrasive particles, and an organic compound having both a carboxylic acid functional group and a second functional group selected from amines and halides. The abrasive particles can be dispersed in the aqueous medium or they can be bonded to the polishing pad.
    Type: Application
    Filed: July 10, 2002
    Publication date: December 26, 2002
    Inventors: Ramanathan Srinivasan, Suryadevara V. Babu, William G. America, Yie-Shein Her
  • Patent number: 6491843
    Abstract: The present invention relates to an aqueous slurry that is particularly useful for removing silicon dioxide in preference to silicon nitride by chemical-mechanical processing. The aqueous slurry according to the invention includes abrasive particles and an organic compound having both a carboxylic acid functional group and a second functional group selected from amines and halides. The present invention also relates to a method of removing silicon dioxide in preference to silicon nitride from a surface of an article by chemical-mechanical polishing. The method includes polishing the surface using a polishing pad, water, abrasive particles, and an organic compound having both a carboxylic acid functional group and a second functional group selected from amines and halides. The abrasive particles can be dispersed in the aqueous medium or they can be bonded to the polishing pad.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: December 10, 2002
    Assignees: Eastman Kodak Company, Clarkson University, Ferro Corporation
    Inventors: Ramanathan Srinivasan, Suryadevara V. Babu, William G. America, Yie-Shein Her
  • Patent number: 6489642
    Abstract: An image sensor, includes a semiconductor substrate; a photosensor having, a first photosensing region including a first stack of one or more layers of transparent materials overlying the substrate, the first photosensing region having a spectral response having peaks and valleys, and a second photosensing region including a second stack of one or more layers of transparent materials overlying the substrate, the second photosensing region having a spectral response having peaks and valleys; and wherein at least one peak or valley of the spectral response of the first region is matched to at least one valley or peak respectively of the spectral response of the second region such that the average spectral response of the photosensor is smoother than the individual spectral response of either the first or second photosensing regions.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: December 3, 2002
    Assignee: Eastman Kodak Company
    Inventors: William G. America, Christopher R. Hoople, Loretta R. Fendrock, Stephen L. Kosman
  • Patent number: 6468910
    Abstract: A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: October 22, 2002
    Inventors: Ramanathan Srinivasan, Suryadevara V. Babu, William G. America, Yie-Shein Her
  • Patent number: 6403993
    Abstract: A method and apparatus of forming adjacent, non-overlapping CCD electrodes within an image sensing device such the electrodes are U-shaped. The device provided by the disclosed method employs a substrate with a gate dielectric layer formed on a surface of the substrate with a plurality of phases created within the CCD. A deposited silicon layer is placed on the surface of the CCD and a mask is used to cover areas other than the first set of electrodes. Etching takes places leaving the mask areas to the deposited silicon and a set of side walls to the remaining deposited silicon are then oxidized. A first set of electrodes by forming an electrode layer placed over the CCD. CMP is employed to remove remaining deposited silicon layer as well as portions of the electrode layer such that the side walls remain vertical portions to electrode layer remaining in the side walls. The process is then repeated by placing another electrode material layer and another CMP process leaving two sets of adjacent U-shaped gates.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: June 11, 2002
    Assignee: Eastman Kodak Company
    Inventors: David L. Losee, William G. America
  • Patent number: 6300160
    Abstract: A method and apparatus of forming adjacent, non-overlapping CCD electrodes within an image sensing device such the electrodes are U-shaped. The device provided by the disclosed method employs a substrate with a gate dielectric layer formed on a surface of the substrate with a plurality of phases created within the CCD. A deposited silicon layer is placed on the surface of the CCD and a mask is used to cover areas other than the first set of electrodes. Etching takes places leaving the mask areas to the deposited silicon and a set of side walls to the remaining deposited silicon are then oxidized. A first set of electrodes by forming an electrode layer placed over the CCD. CMP is employed to remove remaining deposited silicon layer as well as portions of the electrode layer such that the side walls remain vertical portions to electrode layer remaining in the side walls. The process is then repeated by placing another electrode material layer and another CMP process leaving two sets of adjacent U-shaped gates.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: October 9, 2001
    Assignee: Eastman Kodak Company
    Inventors: William G. America, David L. Losee
  • Patent number: 5270125
    Abstract: A laminated structure includes a wafer member with a membrane attached thereto, the membrane being formed of substantially hydrogen-free boron nitride having a nominal composition B.sub.3 N. The structure may be a component in a mechanical device for effecting a mechanical function, or the membrane may form a masking layer on the wafer. The structure includes a body formed of at least two wafer members laminated together with a cavity formed therebetween, with the boron nitride membrane extending into the cavity so as to provide the structural component such as a support for a heating element or a membrane in a gas valve. In another aspect borom is selectively diffused from the boron nitride into a <100> surface of a silicon wafer. The surface is then exposed to EDP etchant to which the diffusion layer is resistant, thereby forming a channel the wafer member with smooth walls for fluid flow.
    Type: Grant
    Filed: October 25, 1991
    Date of Patent: December 14, 1993
    Assignee: Redwood Microsystems, Inc.
    Inventors: William G. America, Richard R. Poole
  • Patent number: 5066533
    Abstract: A laminated structure includes a wafer member with a membrane attached thereto, the membrane being formed of substantially hydrogen-free boron nitride having a nominal composition B.sub.3 N. The structure may be a component in a mechanical device for effecting a mechanical function, or the membrane may form a masking layer on the wafer. The structure includes a body formed of at least two wafer members laminated together with a cavity formed therebetween, with the boron nitride membrane extending into the cavity so as to provide the structural component such as a support for a heating element or a membrane in a gas valve. In another aspect borom is selectively diffused from the boron nitride into a <100> surface of a silicon wafer. The surface is then exposed to EDP etchant to which the diffusion layer is resistant, thereby forming a channel the wafer member with smooth walls for fluid flow.
    Type: Grant
    Filed: June 21, 1990
    Date of Patent: November 19, 1991
    Assignee: The Perkin-Elmer Corporation
    Inventors: William G. America, Richard R. Poole
  • Patent number: 4969938
    Abstract: A microdevice assembly includes a miniature fluid processing device of silicon with a fluid orifice therein. A high-silica glass attachment member sealed to the device has an aperture with a narrow portion aligned with the orifice and a conical portion with a conical wall diverging from the narrow portion. A tube with a soft graphite ferrule thereon is inserted into the conical portion. A rigid package member includes a base supporting the device, a cover disposed proximate the attachment member, and side walls connecting the base and the cover. A threaded opening through the cover is aligned with the aperture. An externally threaded nut with a hole therethrough is fitted slidingly over the tube, and is tightened into the threaded opening so as to sealingly compress the ferrule between the wall and the tube.
    Type: Grant
    Filed: January 3, 1990
    Date of Patent: November 13, 1990
    Assignee: The Perkin-Elmer Corporation
    Inventor: William G. America