Abstract: A passive multi-indicia visual position indicator (30) is used to visually indicate to a user (11) when the user occupies a position that comprises a predetermined desired position with respect to a given object (10). The indicator can be comprised of a single integral structure or can be comprised of a plurality portions. The indicator can comprise any of a wide variety of color and/or graphics related imagery. In one embodiment, the indicator has an annularly-shaped form factor. In one embodiment, the indicator comprises an applique that can be provided in a retrofitting kit that includes appropriate corresponding instructions.

Abstract: Uniformly shaped snack chips, preferably tortilla-type chips, having raised surface features and a method for preparing the same. The chips can be made from a dough composition comprising pre-cooked starch-based material and pregelatinized starch. Preferably, the snack chips have raised surface features comprising from about 12% to about 40% large surface features; from about 20% to about 40% medium surface features; and from about 25% to about 60% small surface features. In one embodiment, the average thickness of the snack chip is from about 1 mm to about 3 mm; the average thickness of raised surface features is from about 2.3 mm to about 3.2 mm; the maximum thickness of the chip is less than about 5.5 mm; and the coefficient of variation of the chip thickness is greater than about 15%.

Abstract: Uniformly shaped snack chips, preferably tortilla-type chips, having raised surface features and a method for preparing the same. The chips can be made from a dough composition comprising pre-cooked starch-based material and pregelatinized starch.

Abstract: Uniformly shaped snack chips, preferably tortilla-type chips, having raised surface features and a method for preparing the same. The chips can be made from a dough composition comprising pre-cooked starch-based material and pregelatinized starch. Preferably, the snack chips have raised surface features comprising from about 12% to about 40% large surface features; from about 20% to about 40% medium surface features; and from about 25% to about 60% small surface features. In one embodiment, the average thickness of the snack chip is from about 1 mm to about 3 mm; the average thickness of raised surface features is from about 2.3 mm to about 3.2 mm; the maximum thickness of the chip is less than about 5.5 mm; and the coefficient of variation of the chip thickness is greater than about 15%.

Abstract: Uniformly shaped snack chips, preferably tortilla-type chips, having raised surface features and a method for preparing the same. The chips can be made from a dough composition comprising pre-cooked starch-based material and pregelatinized starch. Preferably, the snack chips have raised surface features comprising from about 12% to about 40% large surface features; from about 20% to about 40% medium surface features; and from about 25% to about 60% small surface features. In one embodiment, the average thickness of the snack chip is from about 1 mm to about 3 mm; the average thickness of raised surface features is from about 2.3 mm to about 3.2 mm; the maximum thickness of the chip is less than about 5.5 mm; and the coefficient of variation of the chip thickness is greater than about 15%.

Abstract: This shorts test method reduces the occurence of phantom shorts and also in those cases where phantom shorts occur, reduces the time required to eliminate the phantom shorts. When an unexpected open or short occurs or when an expected open or short does not occur, the test is repeated either until the phantom result ceases or until a sufficient time has elapsed that the result is real rather than a transient response. Test points are arranged in an order which decreases monotonically with the parallel impedance of all elements connected directly to that test point. This reduces the rate of occurance of phantom shorts caused by parallel inpedances below the shorts threshold even though none of the individual impedances is below the shorts threshold.

Abstract: A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.

Abstract: A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.

Abstract: A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.

Abstract: A method and apparatus are disclosed for reducing the likelihood of damage to digital logic devices under test or located in close electrical proximity to the device under test while attempting to locate faults in circuit assemblies using digital incircuit test techniques.

Abstract: A two-piece, two chamber self-activating capsule having mercury in one chamber and metal powder in the other. In use, the capsule is shaken and the resulting force due to the inertia of the mercury forces its way through a normally-closed valve into the metal powder chamber, whereby the metal powder and mercury become triturated by the shaking and form dental amalgam for filling teeth. A pestle may be included to facilitate mingling and triturating the amalgam components.

Abstract: An endodontic instrument formed by twisting a tapered blank which in cross section is ground to an oblique parallelogram, the obtuse angles of the oblique parallelogram cross section being between 105.degree.-120.degree..

Abstract: A watchman's tour recording system which includes a watchman's unit having a clock means for producing digital time signals, a station identification signal producing means for producing digital station signals, at least two digital bit storage or memory means and special address means arranged to direct the digital time and station identification signals into predetermined locations in the memory means so that their storage capabilities are most effectively utilized. Novel photoelectric station identification signal generating means are also disclosed.