Abstract: Methods and apparatus are provided for use in manufacturing a device packaging comprising the steps of: positioning a metal substrate such as spring steel on a magnetic plate so as to expose a surface of the metal substrate; placing a first tape layer on the exposed surface of a metal substrate so as to expose a nonstick surface of the first tape layer such as PTFE; placing a second tape layer on the exposed surface of the first tape layer so as to expose a surface of the second tape layer; positioning a mold frame on the exposed surface of the second tape layer; positioning a die within the mold frame; depositing epoxy within the mold frame; curing the epoxy so as to create a molded panel; removing the mold frame; grinding the molded panel to a desired thickness; separating the first tape layer from the second tape layer so as to separate the metal substrate from the molded panel; and peeling the second tape layer from the molded panel.

Abstract: A method for forming a microelectronic assembly is provided. A carrier substrate (30) is provided. A sacrificial layer (38) is formed over the carrier substrate. A polymeric layer (40), including a polymeric tape (42) and a polymeric layer adhesive (44), is formed over the sacrificial layer. The polymeric layer adhesive is between the sacrificial layer and the polymeric tape. A microelectronic die (52), having an integrated circuit formed therein, is placed on the polymeric layer. The microelectronic die is encapsulated with an encapsulation material (54) to form an encapsulated structure (58). The polymeric layer and the encapsulated structure are separated from the carrier substrate. The separating of the polymeric layer and the encapsulated structure includes at least partially deteriorating the sacrificial layer.

Abstract: The invention provides an integrated device with corrosion-resistant capped copper bond pads. The capped copper bond pads include at least one copper bond pad on a semiconductor substrate. An activation layer comprising one of immersion palladium, electroless cobalt, or immersion ruthernium is disposed on the copper bond pad. A first intermediate layer of electroless nickel-boron alloy is disposed on the activation layer. A second intermediate layer comprising one of electroless nickel or electroless palladium is disposed on the first intermediate layer, and an immersion gold layer is disposed on the second intermediate layer. A capped copper bond pad and a method of forming the capped copper bond pads are also disclosed.

Abstract: The invention provides a method of plating an integrated circuit. An activation plate is positioned adjacent to at least one integrated circuit. The integrated circuit includes a plurality of bond pads comprising a bond-pad metal, and the activation plate also comprises the bond-pad metal. A layer of electroless nickel is plated on the bond pads and the activation plate, and a layer of gold is plated over the layer of electroless nickel on the bond pads and the activation plate. An integrated circuit with bond pads plated using the activation plate, and a system for plating an integrated circuit is also disclosed.

Abstract: An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements (340) sealed to a MEMS device die array (300) to produce a sealed MEMS device package array (330). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.

Abstract: A method is disclosed for encapsulating micromechanical elements or features on a substrate. In accordance with the method, a first substrate (111) is provided which has a patterned surface (113). A seed metallization (121) is then deposited onto the patterned surface, and a structural material layer (123), which preferably comprises copper, is electroplated onto the seed metallization. A solder (125), such as SnCu, is electroplated onto the metal layer, and the seed metallization, the structural material layer and the solder are removed from the first substrate as a cohesive structure (127), through the application of heat or by other suitable means, such that a negative replica of the patterned surface is imparted to the structure. The structure may then be placed on a second substrate (129) such that the solder is in contact with the second substrate, after which the solder is reflowed.

Abstract: A method is disclosed for encapsulating micromechanical elements or features on a substrate. In accordance with the method, a first substrate (111) is provided which has a patterned surface (113). A seed metallization (121) is then deposited onto the patterned surface, and a structural material layer (123), which preferably comprises copper, is electroplated onto the seed metallization. A solder (125), such as SnCu, is electroplated onto the metal layer, and the seed metallization, the structural material layer and the solder are removed from the first substrate as a cohesive structure (127), through the application of heat or by other suitable means, such that a negative replica of the patterned surface is imparted to the structure. The structure may then be placed on a second substrate (129) such that the solder is in contact with the second substrate, after which the solder is reflowed.

Abstract: An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements (340) sealed to a MEMS device die array (300) to produce a sealed MEMS device package array (330). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.

Abstract: Apparatus and a method of cold cross-sectioning soft materials includes providing a chuck attached to a drive motor with a composite plate attached to the chuck and including a heat insulating portion, a heat conducting layer, and a central axially extending duct with a plurality of radially extending conduits in communication therewith, the central axially extending duct is accessible externally for introducing a cooling liquid thereto. A sheet of grinding material is magnetically attached to the composite plate and the drive motor is activated to rotate the composite plate and grinding material. A cooling liquid is introduced into the duct and communicated to the conduits and a lubricant is supplied to the exposed rotating surface of grinding material.

Abstract: A bonding structure (10) is formed between a first component (12) and a second component (11) to form a semiconductor device. The bonding structure (10) comprises a bump (24) that has a pedestal region (22) and a crown region (23). The crown region (23) is anchored into a well region (13) of a conductive material (16) that is formed on the second component (11).

Abstract: A method of forming an electrically conductive polymer bump (22) over an aluminum electrode (21) produces low contact resistance for an interconnect structure (24). Aluminum oxide is first removed from the aluminum electrode (21). Tiron and palladium are subsequently bonded to the fresh surface of the aluminum electrode (21). Finally, the electrically conductive polymer bump (22) is formed over the aluminum electrode (21). The Tiron and palladium improve the electrical contact between the conductive polymer bump (22) and the aluminum electrode (21) thereby reducing the contact resistance. The Tiron also inhibits corrosion of the aluminum electrode (21) and enhances the conductivity by catalytically shrinking the cyanate ester conductive bump.

Abstract: A method of forming contact pads (140) that allows for wafer level testing and burn-in of semiconductor die (22). A plurality of semiconductor die (22) are formed upon a semiconductor wafer (20), each semiconductor die (22) having a plurality of bonding pads (78). A contact pad (140) is formed overlying each bonding pad (78) and is electrically coupled to the bonding pad (78) and to wafer test pads (38) through vertical and/or horizontal wafer conductors (42-47 and 52-53 respectively) so that each semiconductor die (22) is uniquely identified. Contact pads (140) protect underlying bonding pads (78) during the formation and removal of vertical and/or horizontal wafer conductors (42-47 and 52-53 respectively). Thus, wafer level electrical testing and/or burn-in can be performed prior to designating a final packaging method for the semiconductor die (22).

Abstract: Interconnect bumps are formed on a circuit substrate using printing or dispensing techniques with a wet photoresist layer as a mask. A conductive paste is disposed in openings of a wet photoresist layer. The conductive paste is at least partially cured before the wet photoresist layer is removed. Alternatively, the wet photoresist layer may remain if it is a photo-imagable polyimide.

Abstract: A plurality of inserts (12) formed on a first substrate (11). A plurality of sockets (14) formed on a second substrate (13). Each socket of the plurality of sockets (14) on the second substrate (13) has a corresponding insert from the plurality of inserts (12) which physically aligns for coupling. At least one of the first (11) or second (13) substrates must be a semiconductor substrate. This arrangement allows for electrically connecting a semiconductor device or structure to another device for testing, burn-in, or final assembly.

Abstract: A method for etching a composite copper layer (40) of plated copper (20) overlying physical vapor deposited copper (30) comprises etching the plated copper (20) at a rate less than the rate of etch of the physical vapor deposited copper (30). The etching may be accomplished with an aqueous solution of ammonium peroxydisulfate with molar concentrations of ammonium ions between 0.0438 and 0.1052, at a temperature between 30.degree. and 35.degree. C. and with the pH buffered to remain at a value between 1 and 1.8.

Abstract: An apparatus plates metal bumps of uniform height on one surface of a semiconductor wafer (32). A plating tank (12) contains the plating solution. The plating solution is filtered (16) and pumped (14) through an inlet (22) to an anode plate (24) within plating cell (20). The anode plate has a solid center area to block direct in-line passage of the plating solution, and concentric rings of openings closer to its perimeter to pass the plating solution. The distance between the inlet and the anode plate is adjustable with supports to create a uniform flow of the plating solution to the surface of the semiconductor wafer for uniform plating of the array of metal bumps (30). The plating cell contains an adjustable sidewall extension (26) to set the proper distance between the anode plate and the semiconductor wafer.

Abstract: A device having a plurality of columnar structures comprised of a solderable metal disposed on a supporting base is used to remove solder from a substrate surface. Capillary action takes place in the area between the columns, thus removing the solder from the substrate surface. The present invention may be fabricated by forming columnar structures on the supporting base through mask openings or by etching a solderable metal layer into columnar structures. A standoff may be built into the device to prevent solder residue from remaining on the substrate surface between solder pads and to allow a controllable amount of solder to be left on the substrate surface.

Abstract: A method for electrolessly plating portions of semiconductor devices and the like comprises the steps of providing a first metal having a higher electromotive series than a coating metal, galvanically coupling a second metal to the first metal wherein a portion of the first metal remains exposed and then subjecting the second metal and the exposed portion of the first metal to an electroless coating metal plating solution. The method employs no masks and is ideal for plating small areas such as single ball bonds and limited numbers of ball bonds on a single semiconductor chip.

Abstract: A backside metalization scheme for semiconductor devices includes a vanadium layer disposed on the backside of a wafer and a silver layer disposed on the vanadium layer. An optional intermediate layer comprising either a mixture of vanadium and silver or nickel may be disposed between the vanadium layer and the silver layer. The vanadium layer exhibits excellent adhesion characteristics on the backside of wafers having a finish at least as fine as a 300 grit equivalency while the silver layer exhibits excellent solderability characteristics.

Abstract: A method of chemically etching TiW and/or TiWN is described wherein the etching of a semiconductor substrate having a layers of TiWN, TiW and Au disposed between the substrate and a Au bump is performed with a 30% solution of hydrogen peroxide (H.sub.2 O.sub.2) at a temperature of approximately 90.degree. C.