Abstract: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

Abstract: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

Abstract: A method of sending an email message having one or more attached files to a plurality of recipients allows customized treatment of each file as it is being sent to each recipient. Treatments may include different types of encryption, plain text transmission, security classification or user-defined treatments. The invention may be implemented in a client-server configuration with separate client and server programs or in a single integrated email program configuration for use on a single computer. The user is presented with a list of recipients, selects a recipient and then selects a treatment for each file to be used when that file is sent to the selected recipient. This process is repeated for each recipient and each file. A control file is generated by the client program, including the recipient information and the file treatment information for each recipient and each file. The client program sends a single copy of the email message, a single copy of each file and the control file to the server program.

Abstract: A method for managing e-mail attachment files received via a network e-mail system by a user. A first e-mail is received at a client computer which includes a first attachment file from the network e-mail system. The client computer begins searching for a second attachment file included with a second e-mail file, preferably automatically after opening the first e-mail. The files are compared to determine if the first attachment file is another incidence of the second attachment file. If true, the method replaces the first attachment file with an identification which points to the second attachment file. When deleting the second e-mail file, the method searches for a third e-mail file. If the third e-mail file is found and the third e-mail file is the next earliest dated incidence of the second e-mail file, the method provides moving and attaching the second attachment file to the third e-mail file.

Abstract: A method and computer program product is described for displaying files associated with multiple hypertext links selected from a Web page. A user selects a set of links from a Web page that contains multiple links, and the linked files are displayed in a preferred sequence without having to repeatedly return to the original Web page. In addition, files associated with these links can be downloaded while the first links are being displayed and viewed by the user. Thus, both the usability and the performance in Web browsing is improved.

Abstract: A method of sending an email message having one or more attached files to a plurality of recipients allows customized treatment of each file as it is being sent to each recipient. Treatments may include different types of encryption, plain text transmission, security classification or user-defined treatments. The invention may be implemented in a client-server configuration with separate client and server programs or in a single integrated email program configuration for use on a single computer. The user is presented with a list of recipients, selects a recipient and then selects a treatment for each file to be used when that file is sent to the selected recipient. This process is repeated for each recipient and each file. A control file is generated by the client program, including the recipient information and the file treatment information for each recipient and each file. The client program sends a single copy of the email message, a single copy of each file and the control file to the server program.

Abstract: A method for managing e-mail attachment files received via a network e-mail system by a user. A first e-mail is received at a client computer which includes a first attachment file from the network e-mail system. The client computer begins searching for a second attachment file included with a second e-mail file, preferably automatically after opening the first e-mail. The files are compared to determine if the first attachment file is another incidence of the second attachment file. If true, the method replaces the first attachment file with an identification which points to the second attachment file. When deleting the second e-mail file, the method searches for a third e-mail file. If the third e-mail file is found and the third e-mail file is the next earliest dated incidence of the second e-mail file, the method provides moving and attaching the second attachment file to the third e-mail file.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.

Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.

Abstract: A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.

Abstract: A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.

Abstract: A structure and process for joining semiconductor components. The present invention allows the flexibility of fabricating electronic components, or semiconductor chip structures, to a common point and electrically joining the different parts together at a back end level, or to a metal wiring level, to complete circuit functionality. Different combinations of front end of the line device chips may be readily joined to a common back end of the line device using a small electrical connection to form a small semiconductor chip package. Instead of packaging different groups of semiconductor chips onto different substrates and then electrically connecting each substrate together for circuit and component functionality, each group of chips can be formed on a single substrate and electrically joined on a back end wafer. These electrically connected and combined groups of chips becomes, for all practical purposes, one chip.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

Abstract: A process sequence for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The process sequence starts with deep trench (DT) processing, followed by deposition of insulator such as SiO2, planarization and pad strip. Then gate insulator and gate conductor are deposited. Also a pad or thin insulator can be deposited at this stage. The structure is etched using a shallow trench isolation mask and filled with SiO.sub.2. The gate conductor such as polysilicon is etched with a contact mask and reactive ion etching. If not previously deposited, a thin insulator is deposited. The structure is etched again with a gate poly contact mask. A gate conductor is then deposited. After a final etch, wiring is added.