Abstract: A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions.

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions and on the polysilicon gate regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; implanting dopants into the source and drain regions for providing deep junctions and into the polysilicon gate regions; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions.

Abstract: A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

Abstract: An electronic package comprising an integrated circuit chip and a flip chip solder bonded thereto is provided. The integrated circuit chip has circuitry over a major surface thereof and has peripheral wire or tab bond pads surrounding an array of C4 connection pads located over this major surface. A flip chip is solder bonded to the C4 connection pads.

Abstract: Ball limited metallurgy is used in conjunction with defining a solder deposit volume using an aperture in a resist layer and reflow of electroplated solder materials deposited in that aperture, possibly with planarization after deposition to enhance volume accuracy, to develop solder deposits extending up to 10 .mu.m or more above the surface on which solder is deposited. Such deposits can be made at fine pitch and provide solder connections of high reliability even when the distance which must be bridged by the solder connection is not easily or reliably regulated.

Abstract: A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

Abstract: An organic polymer resist image layer, formed on a substrate, is stabilized by placing the substrate with the resist image layer in an electrodeless glow discharge in a low pressure fluorine containing atmosphere, for example, CF.sub.4, so as to harden the exposed surface of the layer and then heating the layer.

Abstract: The electrical properties of MIS semiconductor devices, which have been damaged by radiation, are restored by treating the devices in a properly oriented RF field at low pressure.