Patents by Inventor William Hsu

William Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411661
    Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Leonard P. GULER, Vivek THIRTHA, Shu ZHOU, Nitesh KUMAR, Biswajeet GUHA, William HSU, Dax CRUM, Oleg GOLONZKA, Tahir GHANI, Christopher KENYON
  • Publication number: 20200388689
    Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.
    Type: Application
    Filed: February 23, 2018
    Publication date: December 10, 2020
    Inventors: Leonard P. GULER, Biswajeet GUHA, Mark ARMSTRONG, William HSU, Tahir GHANI, Swaminathan SIVAKUMAR
  • Patent number: 10848949
    Abstract: Systems, methods, and devices of the various aspects may enable a mobile communication device to make a second emergency call attempt in a packet switched (PS) domain in response to determining that a first emergency call attempt in a PS domain failed. The various aspects may enable a second emergency call attempt in a PS domain without requiring the mobile communication device to attempt an emergency call in a circuit switched (CS) domain in response to determining that a first emergency call attempt in a PS domain failed.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Osama Lotfallah, Arvind Vardarajan Santhanam, Stephen William Edge, Kuo-Chun Lee, Cherng-Shung Hsu
  • Patent number: 10806314
    Abstract: In one aspect, an autonomous cleaning robot includes a drive configured to propel the robot along the floor surface and a tank assembly. The tank assembly includes a reservoir, left and right receptacles, and a handle extending across a cover of the tank assembly, the handle being moveable between a first position and a second position, wherein when the handle is in the second position, the tank assembly is locked in position. The tank assembly also includes left and right latch assemblies receivable by the left and right receptacles, respectively. Each latch assembly includes a moveable assembly configured to lock the tank assembly in position when the handle is in the second position.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 20, 2020
    Assignee: iRobot Corporation
    Inventors: Jason Jeffrey Suchman, William Farmer, Johnson Hsu
  • Patent number: 10708388
    Abstract: Methods, systems, and devices for defining an action node series at a database system are described. In some examples, the workflow may include one or more nodes are associated with an action. When executed, the workflow may produce an outcome based on the occurrence of an event or parameter associated with the one or more nodes. In some examples, the workflow may include one or more branch nodes. A branch node may include logic such that, when the workflow is executed, the logic selects a particular workflow path that includes its own specific nodes. The path may be selected based on the occurrence of an event or a value of one or more parameters. Thus, when a workflow including one or more branch nodes is executed, the outcome of the workflow may be based on the occurrence of the event or the value of the parameter.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 7, 2020
    Assignee: salesforce.com, inc.
    Inventors: Stephen Hsu, Ashwin Kashyap, Cassandra Funk, Laurel Knell, Eric Berg, Martin Edward Long, Avital Arora, Stanley Lemon, William Victor Gray, Philip Alexander Waligora, Reena Parekh, Kyle Coleman Skibble
  • Publication number: 20200176321
    Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).
    Type: Application
    Filed: August 17, 2017
    Publication date: June 4, 2020
    Applicant: Intel Corporation
    Inventors: Leonard P/ Guler, Biswajeet Guha, Mark Armstrong, Tahir Ghani, William Hsu
  • Publication number: 20200162879
    Abstract: Systems, methods, and devices of the various aspects may enable a mobile communication device to make a second emergency call attempt in a packet switched (PS) domain in response to determining that a first emergency call attempt in a PS domain failed. The various aspects may enable a second emergency call attempt in a PS domain without requiring the mobile communication device to attempt an emergency call in a circuit switched (CS) domain in response to determining that a first emergency call attempt in a PS domain failed.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Inventors: Osama LOTFALLAH, Arvind Vardarajan SANTHANAM, Stephen William EDGE, Kuo-Chun LEE, Cherng-Shung HSU
  • Publication number: 20200105757
    Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Jun Sung KANG, Kai Loon CHEONG, Erica J. THOMPSON, Biswajeet GUHA, William HSU, Dax M. CRUM, Tahir GHANI, Bruce BEATTIE
  • Publication number: 20200099771
    Abstract: Methods, systems, and devices for defining an action node series at a database system are described. In some examples, the workflow may include one or more nodes are associated with an action. When executed, the workflow may produce an outcome based on the occurrence of an event or parameter associated with the one or more nodes. In some examples, the workflow may include one or more branch nodes. A branch node may include logic such that, when the workflow is executed, the logic selects a particular workflow path that includes its own specific nodes. The path may be selected based on the occurrence of an event or a value of one or more parameters. Thus, when a workflow including one or more branch nodes is executed, the outcome of the workflow may be based on the occurrence of the event or the value of the parameter.
    Type: Application
    Filed: December 21, 2018
    Publication date: March 26, 2020
    Inventors: Stephen Hsu, Ashwin Kashyap, Cassandra Funk, Laurel Knell, Eric Berg, Martin Edward Long, Avital Arora, Stanley Lemon, William Victor Gray, Philip Alexander Waligora, Reena Parekh, Kyle Coleman Skibble
  • Publication number: 20200044087
    Abstract: Sub-fin isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the sub-fin isolation schemes include forming one or more dielectric layers between each of the source/drain regions and the substrate. In some such cases, the one or more dielectric layers include material native to the gate sidewall spacers, for example, or other dielectric material. In other cases, the sub-fin isolation schemes include substrate modification that results in oppositely-type doped semiconductor material under each of the source/drain regions and in the sub-fin. The oppositely-type doped semiconductor material results in the interface between that material and each of the source/drain regions being a p-n or n-p junction to block the flow of carriers through the sub-fin. The various sub-fin isolation schemes described herein enable better short channel characteristics for GAA transistors (e.g.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 6, 2020
    Applicant: INTEL CORPORATION
    Inventors: Biswajeet Guha, William Hsu, Tahir Ghani
  • Publication number: 20200030941
    Abstract: This disclosure, in general, relates to nonwoven abrasive belts including flexible butt joints and methods of making and using such belts and joints.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 30, 2020
    Inventors: Zhong XU, Sathanjheri RAVISHANKAR, William C. RICE, Fernando J. RAMIREZ, Jose J. RANGEL, Shyiguei HSU, Ying CAI, Jeremy B. SPENCER
  • Publication number: 20200006525
    Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: DAX M. CRUM, BISWAJEET GUHA, WILLIAM HSU, STEPHEN M. CEA, TAHIR GHANI
  • Publication number: 20200006559
    Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: RISHABH MEHANDRU, STEPHEN M. CEA, BISWAJEET GUHA, TAHIR GHANI, WILLIAM HSU
  • Publication number: 20200006487
    Abstract: Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Biswajeet Guha, Anupama Bowonder, William Hsu, Szuya S. Liao, Mehmet Onur Baykan, Tahir Ghani
  • Publication number: 20200006478
    Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: William Hsu, Biswajeet Guha, Leonard Guler, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie, Tahir Ghani
  • Publication number: 20190393352
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • Publication number: 20190393350
    Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Applicant: INTEL CORPORATION
    Inventors: Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
  • Publication number: 20190393351
    Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-?”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Applicant: INTEL CORPORATION
    Inventors: Bruce E. Beattie, Leonard Guler, Biswajeet Guha, Jun Sung Kang, William Hsu
  • Publication number: 20190355811
    Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea, William Hsu, SZUYA S. LIAO, PRATIK A. PATEL
  • Patent number: 10438347
    Abstract: A system is disclosed using a data-driven approach to objectively measure the diagnostic accuracy and value of diagnostic imaging reports using data captured routinely as part of the electronic health record. The system further utilizes the evaluation of the diagnostic accuracy of individual radiologists (imagers), subspecialty sections, modalities, and entire departments based on a comparison against a “precision diagnosis” rendered by other clinical data sources such as pathology, surgery, laboratory tests, etc.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 8, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Dieter Enzmann, William Hsu, Corey W. Arnold, Alex A. T. Bui