Patents by Inventor William Hsu

William Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294006
    Abstract: Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Chung-Hsun Lin, Biswajeet Guha, William Hsu, Stephen Cea, Tahir Ghani
  • Patent number: 12288789
    Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.
    Type: Grant
    Filed: January 9, 2024
    Date of Patent: April 29, 2025
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani, Kalyan Kolluru, Nathan Jack, Nicholas Thomson, Ayan Kar, Benjamin Orr
  • Publication number: 20250126832
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Applicant: Intel Corporation
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • Patent number: 12272737
    Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: April 8, 2025
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani
  • Patent number: 12224350
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: February 11, 2025
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
  • Publication number: 20250041583
    Abstract: A cardiac assist system includes a pneumatic effector which is implanted beneath a pericardial sac and over a myocardial surface overlying the patient's left ventricle. A port is implanted and receives a percutaneously introduced cannula. The port is connected to supply a driving gas received from the cannula to the pneumatic effector. An external drive unit includes a pump assembly and control circuitry which operate the pump to actuate the pneumatic effector in response to the patient's sensed heart rhythm. A connecting tube has a pump end connected to the pump and a percutaneous port-connecting end attached to the implantable port.
    Type: Application
    Filed: July 10, 2024
    Publication date: February 6, 2025
    Applicant: PercAssist, Inc.
    Inventors: Albert K. CHIN, Gerardo NORIEGA, William HSU
  • Patent number: 12166031
    Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, Brian Greene, Daniel Schulman, William Hsu, Chung-Hsun Lin, Curtis Tsai, Kevin Fischer
  • Publication number: 20240363628
    Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Leonard P. GULER, William HSU, Biswajeet GUHA, Martin WEISS, Apratim DHAR, William T. BLANTON, John H. IRBY, IV, James F. BONDI, Michael K. HARPER, Charles H. WALLACE, Tahir GHANI, Benedict A. SAMUEL, Stefan DICKERT
  • Publication number: 20240347595
    Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.
    Type: Application
    Filed: January 11, 2024
    Publication date: October 17, 2024
    Inventors: William HSU, Biswajeet GUHA, Leonard GULER, Souvik CHAKRABARTY, Jun Sung KANG, Bruce BEATTIE, Tahir GHANI
  • Patent number: 12097364
    Abstract: A cardiac assist system includes a pneumatic effector which is implanted beneath a pericardial sac and over a myocardial surface overlying the patient's left ventricle. A port is implanted and receives a percutaneously introduced cannula. The port is connected to supply a driving gas received from the cannula to the pneumatic effector. An external drive unit includes a pump assembly and control circuitry which operate the pump to actuate the pneumatic effector in response to the patient's sensed heart rhythm. A connecting tube has a pump end connected to the pump and a percutaneous port-connecting end attached to the implantable port.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: September 24, 2024
    Assignee: PERCASSIST, INC.
    Inventors: Albert K. Chin, Gerardo Noriega, William Hsu
  • Patent number: 12068314
    Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, William Hsu, Biswajeet Guha, Martin Weiss, Apratim Dhar, William T. Blanton, John H. Irby, IV, James F. Bondi, Michael K. Harper, Charles H. Wallace, Tahir Ghani, Benedict A. Samuel, Stefan Dickert
  • Publication number: 20240243203
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • Publication number: 20240226562
    Abstract: One aspect of the present disclosure relates to a system for treating a medical condition in a patient. The system can include a neurostimulator that is in electrical communication with a remote transducer. The neurostimulator can be sized and dimensioned for injection or insertion into a pterygopalatine fossa (PPF) of a patient. The remote transducer, when activated and brought into close proximity to the patient's head, can cause the neurostimulator to deliver an electrical signal to a target neural structure located within the PPF to treat the medical condition.
    Type: Application
    Filed: December 18, 2023
    Publication date: July 11, 2024
    Inventors: William Hsu, Anthony Caparso, Thomas Luhrs, Ian G. Welsford, Mark Van Kerkwyk, Vimal Ganesan
  • Publication number: 20240198103
    Abstract: An implantable neurostimulator includes a lead comprising a plurality of electrodes at a distal end, and an implant body including electronics for controlling operation of the electrodes. An electrical connector establishes an electrical connection between the electronics and the electrodes. The implant body includes a first portion of the electrical connector, and the proximal end of the lead includes a second portion of the electrical connector. The first and second portions of the electrical connector are connectable to establish the electrical connection between the electronics and the electrodes. The lead is configured for initial implantation in the patient and the implant body is configured for subsequent implantation in the patient. The electrical connector is configured so that the connection of the first and second portions can be performed with the implant body and the lead positioned at a surgical site in the patient.
    Type: Application
    Filed: February 29, 2024
    Publication date: June 20, 2024
    Inventors: William Hsu, Ian Welsford, Mark Van Kerkwyk, Vimal Ganesan, Bruce Levin
  • Patent number: 12014959
    Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: June 18, 2024
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Biswajeet Guha, Mark Armstrong, Tahir Ghani, William Hsu
  • Publication number: 20240178226
    Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.
    Type: Application
    Filed: February 9, 2024
    Publication date: May 30, 2024
    Inventors: Leonard P. GULER, Michael K. HARPER, William HSU, Biswajeet GUHA, Tahir GHANI, Niels ZUSSBLATT, Jeffrey Miles TAN, Benjamin KRIEGEL, Mohit K. HARAN, Reken PATEL, Oleg GOLONZKA, Mohammad HASAN
  • Patent number: 11990472
    Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt, Jeffrey Miles Tan, Benjamin Kriegel, Mohit K. Haran, Reken Patel, Oleg Golonzka, Mohammad Hasan
  • Publication number: 20240145471
    Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
  • Publication number: 20240145598
    Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Bruce E. BEATTIE, Leonard GULER, Biswajeet GUHA, Jun Sung KANG, William HSU
  • Publication number: 20240120335
    Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Inventors: Sudipto NASKAR, Biswajeet GUHA, William HSU, Bruce BEATTIE, Tahir GHANI