Patents by Inventor William Hsu

William Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220008723
    Abstract: An implantable neurostimulator includes a lead comprising a plurality of electrodes at a distal end, and an implant body including electronics for controlling operation of the electrodes. An electrical connector establishes an electrical connection between the electronics and the electrodes. The implant body includes a first portion of the electrical connector, and the proximal end of the lead includes a second portion of the electrical connector. The first and second portions of the electrical connector are connectable to establish the electrical connection between the electronics and the electrodes. The lead is configured for initial implantation in the patient and the implant body is configured for subsequent implantation in the patient. The electrical connector is configured so that the connection of the first and second portions can be performed with the implant body and the lead positioned at a surgical site in the patient.
    Type: Application
    Filed: May 21, 2021
    Publication date: January 13, 2022
    Inventors: William Hsu, Ian Welsford, Mark Van Kerkwyk, Vilma Ganesan, Bruce Levin
  • Publication number: 20210379357
    Abstract: A cardiac assist system includes a pneumatic effector which is implanted beneath a pericardial sac and over a myocardial surface overlying the patient's left ventricle. A port is implanted and receives a percutaneously introduced cannula. The port is connected to supply a driving gas received from the cannula to the pneumatic effector. An external drive unit includes a pump assembly and control circuitry which operate the pump to actuate the pneumatic effector in response to the patient's sensed heart rhythm. A connecting tube has a pump end connected to the pump and a percutaneous port-connecting end attached to the implantable port.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Applicant: PercAssist, Inc.
    Inventors: Gerardo Noriega, David Tung, Kevin P. McCullogh, William Hsu, Albert K. Chin
  • Patent number: 11164790
    Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Leonard P Guler, Biswajeet Guha, Mark Armstrong, Tahir Ghani, William Hsu
  • Patent number: 11152461
    Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea, William Hsu, Szuya S Liao, Pratik A. Patel
  • Publication number: 20210305430
    Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Inventors: Leonard P. GULER, Stephen SNYDER, Biswajeet GUHA, William HSU, Urusa ALAAN, Tahir GHANI, Michael K. HARPER, Vivek THIRTHA, Shu ZHOU, Nitesh KUMAR
  • Publication number: 20210275814
    Abstract: One aspect of the present disclosure relates to a system for treating a medical condition in a patient. The system can include a neurostimulator that is in electrical communication with a remote transducer. The neurostimulator can be sized and dimensioned for injection or insertion into a pterygopalatine fossa (PPF) of a patient. The remote transducer, when activated and brought into close proximity to the patient's head, can cause the neurostimulator to deliver an electrical signal to a target neural structure located within the PPF to treat the medical condition.
    Type: Application
    Filed: February 23, 2021
    Publication date: September 9, 2021
    Inventors: William Hsu, Anthony Caparso, Thomas Luhrs, Ian Welsford, Mark Van Kerkwyk, Vimal Ganesan
  • Publication number: 20210202479
    Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Inventors: Sudipto NASKAR, Biswajeet GUHA, William HSU, Bruce BEATTIE, Tahir GHANI
  • Publication number: 20210202534
    Abstract: Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Inventors: Chung-Hsun LIN, Biswajeet GUHA, William HSU, Stephen CEA, Tahir GHANI
  • Publication number: 20210202478
    Abstract: Gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfins, and method of fabricating gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfins, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first subfin. A second vertical arrangement of horizontal nanowires is above a second subfin laterally adjacent the first subfin. An isolation structure is laterally between the first subfin and the second subfin, the isolation structure having a maximum height and a maximum width with a maximum height to maximum width ratio of less than 3:1.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Inventors: Biswajeet GUHA, William HSU, Michael HARPER, Leonard P. GULER, Oleg GOLONZKA, Dax M. CRUM, Chung-Hsun LIN, Tahir GHANI
  • Publication number: 20210193652
    Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
  • Publication number: 20210193836
    Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Ayan KAR, Nicholas THOMSON, Benjamin ORR, Nathan JACK, Kalyan KOLLURU, Tahir GHANI
  • Publication number: 20210193807
    Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
  • Publication number: 20210184014
    Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI
  • Patent number: 10939874
    Abstract: An automatic classification method for distinguishing between indolent and clinically significant carcinoma using multiparametric MRI (mp-MRI) imaging is provided. By utilizing a convolutional neural network (CNN), which automatically extracts deep features, the hierarchical classification framework avoids deficiencies in current schemes in the art such as the need to provide handcrafted features predefined by a domain expert and the precise delineation of lesion boundaries by a human or computerized algorithm. This hierarchical classification framework is trained using previously acquired mp-MRI data with known cancer classification characteristics and the framework is applied to mp-MRI images of new patients to provide identification and computerized cancer classification results of a suspicious lesion.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: March 9, 2021
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kyung Hyun Sung, William Hsu, Shiwen Shen, Xinran Zhong
  • Publication number: 20200411661
    Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Leonard P. GULER, Vivek THIRTHA, Shu ZHOU, Nitesh KUMAR, Biswajeet GUHA, William HSU, Dax CRUM, Oleg GOLONZKA, Tahir GHANI, Christopher KENYON
  • Publication number: 20200388689
    Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.
    Type: Application
    Filed: February 23, 2018
    Publication date: December 10, 2020
    Inventors: Leonard P. GULER, Biswajeet GUHA, Mark ARMSTRONG, William HSU, Tahir GHANI, Swaminathan SIVAKUMAR
  • Publication number: 20200176321
    Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).
    Type: Application
    Filed: August 17, 2017
    Publication date: June 4, 2020
    Applicant: Intel Corporation
    Inventors: Leonard P/ Guler, Biswajeet Guha, Mark Armstrong, Tahir Ghani, William Hsu
  • Publication number: 20200105757
    Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Jun Sung KANG, Kai Loon CHEONG, Erica J. THOMPSON, Biswajeet GUHA, William HSU, Dax M. CRUM, Tahir GHANI, Bruce BEATTIE
  • Publication number: 20200044087
    Abstract: Sub-fin isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the sub-fin isolation schemes include forming one or more dielectric layers between each of the source/drain regions and the substrate. In some such cases, the one or more dielectric layers include material native to the gate sidewall spacers, for example, or other dielectric material. In other cases, the sub-fin isolation schemes include substrate modification that results in oppositely-type doped semiconductor material under each of the source/drain regions and in the sub-fin. The oppositely-type doped semiconductor material results in the interface between that material and each of the source/drain regions being a p-n or n-p junction to block the flow of carriers through the sub-fin. The various sub-fin isolation schemes described herein enable better short channel characteristics for GAA transistors (e.g.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 6, 2020
    Applicant: INTEL CORPORATION
    Inventors: Biswajeet Guha, William Hsu, Tahir Ghani
  • Publication number: 20200006487
    Abstract: Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Biswajeet Guha, Anupama Bowonder, William Hsu, Szuya S. Liao, Mehmet Onur Baykan, Tahir Ghani