Patents by Inventor William J. Borland

William J. Borland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100037951
    Abstract: Disclosed are methods of making multi-element, finely divided, metal powders containing one or more reactive metals and one or more non-reactive metals. Reactive metals include metals or mixtures thereof from titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), vanadium (V), nickel (Ni), cobalt (Co), molybdenum (Mo), manganese (Mn), and iron (Fe). Non-reactive metals include metals or mixtures such as silver (Ag), tin (Sn), bismuth (Bi), lead (Pb), antimony (Sb), zinc (Zn), germanium (Ge), phosphorus (P), gold (Au), cadmium (Cd), berrylium (Be), tellurium (Te).
    Type: Application
    Filed: August 12, 2009
    Publication date: February 18, 2010
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventors: William J. Borland, Howard David Glicksman
  • Publication number: 20100037941
    Abstract: Methods and compositions for making photovoltaic devices are provided. A metal that is reactive with silicon is placed in contact with the n-type silicon layer of a silicon substrate. The silicon substrate and reactive metal are fired to form a silicide contact to the n-type silicon layer. A conductive metal electrode is placed in contact with the silicide contact. A silicon solar cell made by such methods is also provided.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 18, 2010
    Applicants: E. I. DU PONT DE NEMOURS AND COMPANY, NORTH CAROLINA STATE UNIVERSITY
    Inventors: WILLIAM J. BORLAND, Jon-Paul Maria
  • Patent number: 7613007
    Abstract: The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: November 3, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Daniel Irwin Amey, Jr., Sounak Banerji, William J. Borland, Karl Hartmann Dietz, David Ross McGregor, Attiganal N. Sreeram
  • Patent number: 7586198
    Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 8, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Matthew C. Snogren, Richard H. Snogren
  • Patent number: 7531416
    Abstract: Thick-film capacitors are formed on ceramic interconnect substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are fired at high temperatures.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: May 12, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Daniel Irwin Amey, Jr., William J. Borland
  • Publication number: 20080297274
    Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.
    Type: Application
    Filed: August 8, 2008
    Publication date: December 4, 2008
    Inventors: WILLIAM J. BORLAND, G. Sidney Cox, David Ross McGregor
  • Patent number: 7430128
    Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode, a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0. This invention also relates to a method of making the device.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: September 30, 2008
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: William J. Borland, G. Sidney Cox, David Ross McGregor
  • Publication number: 20080145995
    Abstract: Making process test capacitors simultaneously with circuit capacitors that are to be embedded into a printed wiring board and firing the test capacitors to result in fired-on-foil test capacitors for the purpose of using the test capacitors as test substitutes for the embedded circuit capacitors to predict whether capacitance, dissipation factor or insulation resistance of the circuit capacitors will fall within acceptable specified ranges prior to and after embedment.
    Type: Application
    Filed: December 18, 2006
    Publication date: June 19, 2008
    Applicant: E.I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Daniel I. Amey
  • Patent number: 7382627
    Abstract: A capacitive/resistive device provides both resistive and capacitive functions. The capacitive/resistive device may be embedded within a layer of a printed wiring board. Embedding the capacitive/resistive device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. Conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: June 3, 2008
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: William J. Borland, G. Sidney Cox, David Ross McGregor
  • Publication number: 20080037198
    Abstract: Disclosed is a method of forming individual thin-film capacitors for embedding inside printed wiring boards or organic semiconductor package substrates, which includes removal of selective portions of the capacitor by sandblasting or other means so that the ceramic dielectric does not come in contact with acid etching solutions.
    Type: Application
    Filed: August 10, 2006
    Publication date: February 14, 2008
    Inventors: William J. Borland, David Ross McGregor, Daniel Irwin Amey, Matthew T. Onken
  • Publication number: 20080010798
    Abstract: Methods of making capacitors are disclosed that comprise forming a dielectric layer over a substrate with a first electrode or a bare metallic foil, depositing a top conductive layer over the dielectric layer, and annealing the dielectric layer and the top conductive layer wherein the foil or first electrode, the dielectric, and the conductive layer form a capacitor.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 17, 2008
    Inventors: William J. Borland, Patrick Daniels, Dean W. Face, Jon Fredrick Ihlefeld, Jon-Paul Maria
  • Patent number: 7256980
    Abstract: Thin-film capacitors are formed on ceramic substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are annealed at high temperatures.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: August 14, 2007
    Inventor: William J. Borland
  • Patent number: 7178229
    Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: February 20, 2007
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Matthew C. Snogren, Richard H. Snogren
  • Patent number: 7100277
    Abstract: A method of forming printed wiring boards having embedded thick-film capacitors includes covering capacitor layers with a protective coating prior to etching to prevent etching solutions from contacting with and damaging the capacitor layers and forming vias directly between the capacitor electrodes and the board circuitry.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: September 5, 2006
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Hena Pyada
  • Patent number: 7072167
    Abstract: A capacitor structure is fabricated by forming a pattern of first dielectrics over a foil, forming first electrodes over the first dielectrics, and co-firing the first dielectrics and the first electrodes. Co-firing of the dielectrics and the electrodes alleviates cracking caused by differences in thermal coefficient of expansion (TCE) between the electrodes and the dielectrics. Co-firing also ensures a strong bond between the dielectrics and the electrodes. In addition, co-firing allows multi-layer capacitor structures to be constructed, and allows the capacitor electrodes to be formed from copper.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: July 4, 2006
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: William J. Borland
  • Patent number: 7029971
    Abstract: Dielectrics are formed having high dielectric constants, low loss tangents, and other desirable electrical and physical properties. The dielectrics are annealed at temperatures allowing the use of copper foil substrates, and at low oxygen partial pressures.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: April 18, 2006
    Assignees: E. I. du Pont de Nemours and Company, Norch Carolina State University
    Inventors: William J. Borland, Jon Fredrick Ihlefeld, Angus Ian Kingon, Jon-Paul Maria
  • Publication number: 20040231885
    Abstract: In a printed wiring board, a plurality of stacked innerlayer panels have capacitors connected in parallel by connecting a first electrode of a first panel with a first electrode of a second panel, and similarly connecting second electrodes of the first and second panels. The innerlayer panel having capacitors connected in parallel provides a high capacitance in a small x-y area. An alternate printed wiring board has a capacitor having a first foil electrode, and second and third electrodes located on opposite sides of the first foil electrode. Yet another printed wiring board has capacitors formed as an array of discrete foil electrodes spaced from an array of discrete printed electrodes. Forming discrete interconnected electrodes allows the electrodes to be fired without excessive thermal coefficient of expansion stresses damaging the electrodes.
    Type: Application
    Filed: February 4, 2004
    Publication date: November 25, 2004
    Inventors: William J. Borland, Saul Ferguson, David R. McGregor
  • Publication number: 20040233611
    Abstract: A capacitor structure is fabricated by forming a pattern of first dielectrics over a foil, forming first electrodes over the first dielectrics, and co-firing the first dielectrics and the first electrodes. Co-firing of the dielectrics and the electrodes alleviates cracking caused by differences in thermal coefficient of expansion (TCE) between the electrodes and the dielectrics. Co-firing also ensures a strong bond between the dielectrics and the electrodes. In addition, co-firing allows multi-layer capacitor structures to be constructed, and allows the capacitor electrodes to be formed from copper.
    Type: Application
    Filed: June 28, 2004
    Publication date: November 25, 2004
    Inventor: William J. Borland
  • Publication number: 20040108134
    Abstract: A printed wiring board (PWB) has stacked innerlayer panels comprised of passive circuit elements. The passive elements can include capacitors with electrode terminations located within the footprints of the capacitor electrodes. The capacitor terminations are therefore closely spaced, reducing the capacitors' contributions to loop inductance in the innerlayer. Capacitor terminations within the electrode footprints also reduce the PWB board surface area used in forming the capacitors.
    Type: Application
    Filed: September 16, 2003
    Publication date: June 10, 2004
    Inventors: William J. Borland, Saul Ferguson, David R. McGregor
  • Publication number: 20040099999
    Abstract: A capacitor structure is fabricated by forming a pattern of first dielectrics over a foil, forming first electrodes over the first dielectrics, and co-firing the first dielectrics and the first electrodes. Co-firing of the dielectrics and the electrodes alleviates cracking caused by differences in thermal coefficient of expansion (TCE) between the electrodes and the dielectrics. Co-firing also ensures a strong bond between the dielectrics and the electrodes. In addition, co-firing allows multi-layer capacitor structures to be constructed, and allows the capacitor electrodes to be formed from copper.
    Type: Application
    Filed: August 29, 2003
    Publication date: May 27, 2004
    Inventor: William J. Borland