Patents by Inventor William J. Dauksher
William J. Dauksher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120214047Abstract: Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.Type: ApplicationFiled: May 1, 2012Publication date: August 23, 2012Applicants: Motorola Mobility, Inc., Applied Materials, Inc.Inventors: BYUNG SUNG KWAK, Nety M. Krishna, Kurt Eisenbeiser, William J. Dauksher, Jon Candelaria
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Patent number: 8198705Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.Type: GrantFiled: September 16, 2008Date of Patent: June 12, 2012Assignee: Freescale Semiconductor, Inc.Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Weston, Steven R. Young, Robert W. Baird
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Patent number: 8168318Abstract: Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.Type: GrantFiled: October 23, 2008Date of Patent: May 1, 2012Assignees: Applied Materials, Inc., Motorola Mobility, Inc.Inventors: Byung Sung Kwak, Nety M. Krishna, Kurt Eisenbeiser, William J. Dauksher, Jon Candelaria
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Publication number: 20090148764Abstract: Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.Type: ApplicationFiled: October 23, 2008Publication date: June 11, 2009Applicants: APPLIED MATERIALS, INC., MOTOROLA, INC.Inventors: Byung Sung Kwak, Nety M. Krishna, Kurt Eisenbelser, William J. Dauksher, Jon Candelaria
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Patent number: 7507638Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.Type: GrantFiled: June 30, 2004Date of Patent: March 24, 2009Assignee: Freescale Semiconductor, Inc.Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Weston, Steven R. Young, Robert W. Baird
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Publication number: 20090008748Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.Type: ApplicationFiled: September 16, 2008Publication date: January 8, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Watson, Steven R. Young, Robert W. Baird
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Patent number: 7432024Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), a transparent conductive layer (16) formed on a surface (14) of the substrate (12) by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer (20) formed on a surface (18) of the transparent conductive layer (16).Type: GrantFiled: June 12, 2006Date of Patent: October 7, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Albert Alec Talin, Jeffrey H. Baker, William J. Dauksher, Andy Hooper, Douglas J. Resnick
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Patent number: 7425392Abstract: A lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template is provided. The lithographic template (10) and the method of making comprises forming a transparent conductive layer (16) over a substrate (12). A SiCN layer (18) is formed over the transparent conductive layer (16), and a patterning layer (20) formed on the SiCN layer (18). The SiCN layer (18) is converted to an SiO2 layer by applying an O2 plasma (23). The SiO2 layer prevents damage to the transparent conductive layer (16) during cleaning and provides a binding mechanism for the imprint release coating.Type: GrantFiled: August 26, 2005Date of Patent: September 16, 2008Assignee: Motorola, Inc.Inventors: Kevin J. Nordquist, Jeffrey H. Baker, William J. Dauksher
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Patent number: 7413924Abstract: A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.Type: GrantFiled: October 31, 2005Date of Patent: August 19, 2008Assignee: Motorola, Inc.Inventors: Donald F. Weston, William J. Dauksher, Emmett M. Howard
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Publication number: 20080003485Abstract: A method is provided for patterning a solid proton conducting electrolyte (22, 60) for a micro fuel cell. The method comprises patterning a first side (30, 63) of a solid proton conducting electrolyte (22, 60) to increase the surface area, coating the patterned first side (22, 60) with an electrocatalyst (33, 66), providing a first electrical conductor (20) to the first side (22, 60), and providing a second electrical conductor (15, 16) to a second side (19) of the solid proton conducting electrolyte (22, 60) opposed to the first side (22, 60).Type: ApplicationFiled: June 30, 2006Publication date: January 3, 2008Inventors: Ramkumar Krishnan, William J. Dauksher, Chowdary R. Koripella
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Patent number: 7163888Abstract: A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the substrate; and performing (48) an etch to substantially remove the residual layer. Optionally, a patterning layer (52) may be formed on the substrate (12) prior to forming the etch barrier layer (14). Additionally, an adhesive layer (13) may be applied (42) between the substrate (12) and the etch barrier layer (14).Type: GrantFiled: November 22, 2004Date of Patent: January 16, 2007Assignee: Motorola, Inc.Inventors: Kathy A. Gehoski, William J. Dauksher, Ngoc V. Le, Douglas J. Resnick
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Patent number: 7125796Abstract: A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer 14 and etching through the dielectric layer 14 and the organic bonding material 32 with 60CF4/20Ar/60CHF3/20N2. The resist may then be removed with an anisotropic high density oxygen plasma.Type: GrantFiled: November 30, 2004Date of Patent: October 24, 2006Assignee: Motorola, Inc.Inventors: Donald F. Weston, William J. Dauksher, Ngoc V. Le
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Patent number: 7083880Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), a transparent conductive layer (16) formed on a surface (14) of the substrate (12) by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer (20) formed on a surface (18) of the transparent conductive layer (16).Type: GrantFiled: August 15, 2002Date of Patent: August 1, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Albert Alec Talin, Jeffrey H. Baker, William J. Dauksher, Andy Hooper, Douglas J. Resnick
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Patent number: 7063919Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to an improved lithographic template including a repaired defect, a method of fabricating the improved lithographic template, a method for repairing defects present in the template, and a method for making semiconductor devices with the improved lithographic template. The lithographic template (10) is formed having a relief structure (26) and a repaired gap defect (36) within the relief structure (26). The template (10) is used in the fabrication of a semiconductor device (40) for affecting a pattern in device (40) by positioning the template (10) in close proximity to semiconductor device (40) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief structure present on the template.Type: GrantFiled: July 31, 2002Date of Patent: June 20, 2006Inventors: David P. Mancini, William J. Dauksher, Kevin J. Nordquist, Douglas J. Resnick
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Patent number: 6797440Abstract: A semiconductor device is formed by patterning a resist layer using a rim phase shifting mask. A multilayer or single patterning layer to form the different phase-shifting regions and opaque regions is used to manufacture the rim phase shifting mask. First phase shifting regions are formed by transferring an opening in the multilayer or single patterning layer through an opaque layer and a transparent substrate. At least portions of the same multilayer or single patterning layer are used to recess the opaque layer a predetermined distance to form rims (second phase shifting regions). The first phase-shifting regions phase shift the light traveling through them 180 degrees relative to the light traveling through the rims, thereby increasing the contrast of the light traveling through the rim phase shifting mask.Type: GrantFiled: August 6, 2002Date of Patent: September 28, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Cesar M. Garza, Wei E. Wu, Bernard J. Roman, Pawitter J. S. Mangat, Kevin J. Nordquist, William J. Dauksher
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Publication number: 20040033424Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), a transparent conductive layer (16) formed on a surface (14) of the substrate (12) by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer (20) formed on a surface (18) of the transparent conductive layer (16).Type: ApplicationFiled: August 15, 2002Publication date: February 19, 2004Inventors: Albert Alec Talin, Jeffrey H. Baker, William J. Dauksher, Andy Hooper, Douglas J. Resnick
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Publication number: 20040029021Abstract: A semiconductor device is formed by patterning a resist layer using a rim phase shifting mask. A multilayer or single patterning layer to form the different phase-shifting regions and opaque regions is used to manufacture the rim phase shifting mask. First phase shifting regions are formed by transferring an opening in the multilayer or single patterning layer through an opaque layer and a transparent substrate. At least portions of the same multilayer or single patterning layer are used to recess the opaque layer a predetermined distance to form rims (second phase shifting regions). The first phase-shifting regions phase shift the light traveling through them 180 degrees relative to the light traveling through the rims, thereby increasing the contrast of the light traveling through the rim phase shifting mask.Type: ApplicationFiled: August 6, 2002Publication date: February 12, 2004Inventors: Cesar M. Garza, Wei E. Wu, Bernard J. Roman, Pawitter J. S. Mangat, Kevin J. Nordquist, William J. Dauksher
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Publication number: 20040023126Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to an improved lithographic template including a repaired defect, a method of fabricating the improved lithographic template, a method for repairing defects present in the template, and a method for making semiconductor devices with the improved lithographic template. The lithographic template (10) is formed having a relief structure (26) and a repaired gap defect (36) within the relief structure (26). The template (10) is used in the fabrication of a semiconductor device (40) for affecting a pattern in device (40) by positioning the template (10) in close proximity to semiconductor device (40) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief structure present on the template.Type: ApplicationFiled: July 31, 2002Publication date: February 5, 2004Inventors: David P. Mancini, William J. Dauksher, Kevin J. Nordquist, Douglas J. Resnick
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Patent number: 6580172Abstract: The lithographic template is formed having a substrate, an optional etch stop layer formed on a surface of the substrate, and a patterning layer formed on a surface of the etch stop layer. The template is used in the fabrication of a semiconductor device for affecting a pattern in the device by positioning the template in close proximity to the semiconductor device having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template. Radiation is then applied through the template so as to further cure portions of the radiation sensitive material and further define the pattern in the radiation sensitive material. The template is then removed to complete fabrication of the semiconductor device.Type: GrantFiled: March 21, 2002Date of Patent: June 17, 2003Assignee: Motorola, Inc.Inventors: David P. Mancini, Doug J. Resnick, William J. Dauksher
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Publication number: 20020122995Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), an optional etch stop layer (16) formed on a surface (14) of the substrate (12), and a patterning layer (20) formed on a surface (18) of the etch stop layer (16). The template (10) is used in the fabrication of a semiconductor device (30) for affecting a pattern in device (30) by positioning the template (10) in close proximity to semiconductor device (30) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template.Type: ApplicationFiled: March 21, 2002Publication date: September 5, 2002Inventors: David P. Mancini, Doug J. Resnick, William J. Dauksher