Patents by Inventor William J. Dauksher

William J. Dauksher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120214047
    Abstract: Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.
    Type: Application
    Filed: May 1, 2012
    Publication date: August 23, 2012
    Applicants: Motorola Mobility, Inc., Applied Materials, Inc.
    Inventors: BYUNG SUNG KWAK, Nety M. Krishna, Kurt Eisenbeiser, William J. Dauksher, Jon Candelaria
  • Patent number: 8198705
    Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 12, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Weston, Steven R. Young, Robert W. Baird
  • Patent number: 8168318
    Abstract: Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: May 1, 2012
    Assignees: Applied Materials, Inc., Motorola Mobility, Inc.
    Inventors: Byung Sung Kwak, Nety M. Krishna, Kurt Eisenbeiser, William J. Dauksher, Jon Candelaria
  • Publication number: 20090148764
    Abstract: Concepts and methods are provided to reduce the cost and complexity of thin film battery (TFB) high volume manufacturing by eliminating and/or minimizing the use of conventional physical (shadow) masks. Laser scribing and other alternative physical maskless patterning techniques meet certain or all of the patterning requirements. In one embodiment, a method of manufacturing thin film batteries comprises providing a substrate, depositing layers corresponding to a thin film battery structure on the substrate, the layers including, in order of deposition, a cathode, an electrolyte and an anode, wherein at least one of the deposited layers is unpatterned by a physical mask during deposition, depositing a protective coating, and scribing the layers and the protective coating. Further, the edges of the layers may be covered by an encapsulation layer. Furthermore, the layers may be deposited on two substrates and then laminated to form the thin film battery.
    Type: Application
    Filed: October 23, 2008
    Publication date: June 11, 2009
    Applicants: APPLIED MATERIALS, INC., MOTOROLA, INC.
    Inventors: Byung Sung Kwak, Nety M. Krishna, Kurt Eisenbelser, William J. Dauksher, Jon Candelaria
  • Patent number: 7507638
    Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: March 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Weston, Steven R. Young, Robert W. Baird
  • Publication number: 20090008748
    Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.
    Type: Application
    Filed: September 16, 2008
    Publication date: January 8, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: David P. Mancini, Young Sir Chung, William J. Dauksher, Donald F. Watson, Steven R. Young, Robert W. Baird
  • Patent number: 7432024
    Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), a transparent conductive layer (16) formed on a surface (14) of the substrate (12) by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer (20) formed on a surface (18) of the transparent conductive layer (16).
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: October 7, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Albert Alec Talin, Jeffrey H. Baker, William J. Dauksher, Andy Hooper, Douglas J. Resnick
  • Patent number: 7425392
    Abstract: A lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template is provided. The lithographic template (10) and the method of making comprises forming a transparent conductive layer (16) over a substrate (12). A SiCN layer (18) is formed over the transparent conductive layer (16), and a patterning layer (20) formed on the SiCN layer (18). The SiCN layer (18) is converted to an SiO2 layer by applying an O2 plasma (23). The SiO2 layer prevents damage to the transparent conductive layer (16) during cleaning and provides a binding mechanism for the imprint release coating.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: September 16, 2008
    Assignee: Motorola, Inc.
    Inventors: Kevin J. Nordquist, Jeffrey H. Baker, William J. Dauksher
  • Patent number: 7413924
    Abstract: A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 19, 2008
    Assignee: Motorola, Inc.
    Inventors: Donald F. Weston, William J. Dauksher, Emmett M. Howard
  • Publication number: 20080003485
    Abstract: A method is provided for patterning a solid proton conducting electrolyte (22, 60) for a micro fuel cell. The method comprises patterning a first side (30, 63) of a solid proton conducting electrolyte (22, 60) to increase the surface area, coating the patterned first side (22, 60) with an electrocatalyst (33, 66), providing a first electrical conductor (20) to the first side (22, 60), and providing a second electrical conductor (15, 16) to a second side (19) of the solid proton conducting electrolyte (22, 60) opposed to the first side (22, 60).
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Ramkumar Krishnan, William J. Dauksher, Chowdary R. Koripella
  • Patent number: 7163888
    Abstract: A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the substrate; and performing (48) an etch to substantially remove the residual layer. Optionally, a patterning layer (52) may be formed on the substrate (12) prior to forming the etch barrier layer (14). Additionally, an adhesive layer (13) may be applied (42) between the substrate (12) and the etch barrier layer (14).
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: January 16, 2007
    Assignee: Motorola, Inc.
    Inventors: Kathy A. Gehoski, William J. Dauksher, Ngoc V. Le, Douglas J. Resnick
  • Patent number: 7125796
    Abstract: A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer 14 and etching through the dielectric layer 14 and the organic bonding material 32 with 60CF4/20Ar/60CHF3/20N2. The resist may then be removed with an anisotropic high density oxygen plasma.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: October 24, 2006
    Assignee: Motorola, Inc.
    Inventors: Donald F. Weston, William J. Dauksher, Ngoc V. Le
  • Patent number: 7083880
    Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), a transparent conductive layer (16) formed on a surface (14) of the substrate (12) by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer (20) formed on a surface (18) of the transparent conductive layer (16).
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: August 1, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Albert Alec Talin, Jeffrey H. Baker, William J. Dauksher, Andy Hooper, Douglas J. Resnick
  • Patent number: 7063919
    Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to an improved lithographic template including a repaired defect, a method of fabricating the improved lithographic template, a method for repairing defects present in the template, and a method for making semiconductor devices with the improved lithographic template. The lithographic template (10) is formed having a relief structure (26) and a repaired gap defect (36) within the relief structure (26). The template (10) is used in the fabrication of a semiconductor device (40) for affecting a pattern in device (40) by positioning the template (10) in close proximity to semiconductor device (40) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief structure present on the template.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: June 20, 2006
    Inventors: David P. Mancini, William J. Dauksher, Kevin J. Nordquist, Douglas J. Resnick
  • Patent number: 6797440
    Abstract: A semiconductor device is formed by patterning a resist layer using a rim phase shifting mask. A multilayer or single patterning layer to form the different phase-shifting regions and opaque regions is used to manufacture the rim phase shifting mask. First phase shifting regions are formed by transferring an opening in the multilayer or single patterning layer through an opaque layer and a transparent substrate. At least portions of the same multilayer or single patterning layer are used to recess the opaque layer a predetermined distance to form rims (second phase shifting regions). The first phase-shifting regions phase shift the light traveling through them 180 degrees relative to the light traveling through the rims, thereby increasing the contrast of the light traveling through the rim phase shifting mask.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: September 28, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cesar M. Garza, Wei E. Wu, Bernard J. Roman, Pawitter J. S. Mangat, Kevin J. Nordquist, William J. Dauksher
  • Publication number: 20040033424
    Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), a transparent conductive layer (16) formed on a surface (14) of the substrate (12) by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer (20) formed on a surface (18) of the transparent conductive layer (16).
    Type: Application
    Filed: August 15, 2002
    Publication date: February 19, 2004
    Inventors: Albert Alec Talin, Jeffrey H. Baker, William J. Dauksher, Andy Hooper, Douglas J. Resnick
  • Publication number: 20040029021
    Abstract: A semiconductor device is formed by patterning a resist layer using a rim phase shifting mask. A multilayer or single patterning layer to form the different phase-shifting regions and opaque regions is used to manufacture the rim phase shifting mask. First phase shifting regions are formed by transferring an opening in the multilayer or single patterning layer through an opaque layer and a transparent substrate. At least portions of the same multilayer or single patterning layer are used to recess the opaque layer a predetermined distance to form rims (second phase shifting regions). The first phase-shifting regions phase shift the light traveling through them 180 degrees relative to the light traveling through the rims, thereby increasing the contrast of the light traveling through the rim phase shifting mask.
    Type: Application
    Filed: August 6, 2002
    Publication date: February 12, 2004
    Inventors: Cesar M. Garza, Wei E. Wu, Bernard J. Roman, Pawitter J. S. Mangat, Kevin J. Nordquist, William J. Dauksher
  • Publication number: 20040023126
    Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to an improved lithographic template including a repaired defect, a method of fabricating the improved lithographic template, a method for repairing defects present in the template, and a method for making semiconductor devices with the improved lithographic template. The lithographic template (10) is formed having a relief structure (26) and a repaired gap defect (36) within the relief structure (26). The template (10) is used in the fabrication of a semiconductor device (40) for affecting a pattern in device (40) by positioning the template (10) in close proximity to semiconductor device (40) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief structure present on the template.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 5, 2004
    Inventors: David P. Mancini, William J. Dauksher, Kevin J. Nordquist, Douglas J. Resnick
  • Patent number: 6580172
    Abstract: The lithographic template is formed having a substrate, an optional etch stop layer formed on a surface of the substrate, and a patterning layer formed on a surface of the etch stop layer. The template is used in the fabrication of a semiconductor device for affecting a pattern in the device by positioning the template in close proximity to the semiconductor device having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template. Radiation is then applied through the template so as to further cure portions of the radiation sensitive material and further define the pattern in the radiation sensitive material. The template is then removed to complete fabrication of the semiconductor device.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: June 17, 2003
    Assignee: Motorola, Inc.
    Inventors: David P. Mancini, Doug J. Resnick, William J. Dauksher
  • Publication number: 20020122995
    Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), an optional etch stop layer (16) formed on a surface (14) of the substrate (12), and a patterning layer (20) formed on a surface (18) of the etch stop layer (16). The template (10) is used in the fabrication of a semiconductor device (30) for affecting a pattern in device (30) by positioning the template (10) in close proximity to semiconductor device (30) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template.
    Type: Application
    Filed: March 21, 2002
    Publication date: September 5, 2002
    Inventors: David P. Mancini, Doug J. Resnick, William J. Dauksher