Patents by Inventor William J. Gallagher

William J. Gallagher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031544
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a superparamagnetic free layer overlying the non-magnetic barrier layer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, William J. Gallagher
  • Publication number: 20210143375
    Abstract: A gas engine replacement device includes a housing, a battery receptacle coupled to the housing to receive a battery pack, a motor within the housing, a power take-off shaft receiving torque from the motor and protruding from a side of the housing, a power switching network configured to provide power from the battery pack to the motor, and an electronic processor coupled to the power switching network and configured to control the power switching network to rotate the motor and to receive a command speed, determine whether the command speed is in an exclusion zone, set an output speed at the command speed responsive to the command speed being outside the exclusion zone, set the output speed to a speed outside the exclusion zone responsive to the command speed being in the exclusion zone, and control the power switching network to rotate the motor in accordance with the output speed.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 13, 2021
    Inventors: Timothy R. Obermann, David W. Siegler, Alexander Huber, William F. Chapman, III, Patrick D. Gallagher, Timothy J. Bartlett
  • Patent number: 11000941
    Abstract: The present disclosure is directed to a cordless reciprocating saw including a mechanical interface for attaching a removable battery pack. The mechanical interface includes a strike plate to reduce the effects of vibrational forces on the battery pack.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 11, 2021
    Assignee: Black & Decker Inc.
    Inventors: Benjamin Krupsaw, Paul S. White, Michael Varipatis, Nathan J. Osborne, Nicholas J. Garibaldi, Christian V. Elder, William F. Gallagher
  • Publication number: 20210135098
    Abstract: Some examples relate to a method for forming a semiconductor device. The method comprises forming a pattern definition stack over a substrate, the pattern definition stack comprising a transfer layer, an interlayer arranged over the transfer layer, and a patterning layer arranged over the interlayer. The method further comprises forming a first opening in the patterning layer to expose an upper surface of the interlayer and etching the interlayer with an at least partially isotropic etchant through the first opening to form a recessed cavity. The method further comprises forming a conformal layer over the interlayer and the patterning layer to fill the first opening, and etching the conformal layer and the transfer layer with an anisotropic etch to form a second opening in the transfer layer. The method also comprises depositing a hard mask material in the second opening.
    Type: Application
    Filed: March 23, 2020
    Publication date: May 6, 2021
    Inventor: William J. Gallagher
  • Publication number: 20210122659
    Abstract: A system and method for synchronized oxy-fuel boosting of a regenerative glass melting furnace including first and second sets of regenerative air-fuel burners, a first double-staged oxy-fuel burner mounted in a first wall, and a second double-staged oxy-fuel burner mounted in a second wall, each oxy-fuel burner having a primary oxygen valve to apportion a flow of oxygen between primary oxygen and staged oxygen and a staging mode valve to apportion the flow of staged oxygen between an upper staging port and a lower staging port in the respective burner, and a controller programmed to control the primary oxygen valve and the staging mode valve of each of the first and second oxy-fuel burners to adjust flame characteristics of the first and second oxy-fuel burners depending on the state of operation of the furnace.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 29, 2021
    Applicant: Air Products and Chemicals, Inc.
    Inventors: Mark Daniel D'Agostini, Michael J. Gallagher, William J. Horan
  • Patent number: 10971576
    Abstract: An on-chip magnetic structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Andrew J. Kellock, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • Publication number: 20210036054
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a shunting layer overlying a spin orbit torque (SOT) layer. A magnetic tunnel junction (MTJ) structure overlies a semiconductor substrate. The MTJ structure includes a free layer, a reference layer, and a tunnel barrier layer disposed between the free and reference layers. A bottom electrode via (BEVA) underlies the MTJ structure, where the BEVA is laterally offset from the MTJ structure by a lateral distance. The SOT layer is disposed vertically between the BEVA and the MTJ structure, where the SOT layer continuously extends along the lateral distance. The shunting layer extends across an upper surface of the SOT layer and extends across at least a portion of the lateral distance.
    Type: Application
    Filed: December 23, 2019
    Publication date: February 4, 2021
    Inventors: William J. Gallagher, Shy-Jay Lin, Ming Yuan Song
  • Patent number: 10784045
    Abstract: A technique relates to a method of forming a laminated multilayer magnetic structure. An adhesion layer is deposited on a substrate. A magnetic seed layer is deposited on top of the adhesion layer. Magnetic layers and non-magnetic spacer layers are alternatingly deposited such that an even number of the magnetic layers is deposited while an odd number of the non-magnetic spacer layers is deposited. The odd number is one less than the even number. Every two of the magnetic layers is separated by one of the non-magnetic spacer layers. The first of the magnetic layers is deposited on the magnetic seed layer, and the magnetic layers each have a thickness less than 500 nanometers.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Sathana Kitayaporn, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang, Joonah Yoon
  • Patent number: 10763038
    Abstract: A technique relates to a method of forming a laminated multilayer magnetic structure. An adhesion layer is deposited on a substrate. A magnetic seed layer is deposited on top of the adhesion layer. Magnetic layers and non-magnetic spacer layers are alternatingly deposited such that an even number of the magnetic layers is deposited while an odd number of the non-magnetic spacer layers is deposited. The odd number is one less than the even number. Every two of the magnetic layers is separated by one of the non-magnetic spacer layers. The first of the magnetic layers is deposited on the magnetic seed layer, and the magnetic layers each have a thickness less than 500 nanometers.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Sathana Kitayaporn, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang, Joonah Yoon
  • Publication number: 20200152865
    Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode. The second insulating cover layer has an oxygen getter property.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Shy-Jay LIN, Chwen YU, William J. GALLAGHER
  • Publication number: 20200106001
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a superparamagnetic free layer overlying the non-magnetic barrier layer.
    Type: Application
    Filed: July 9, 2019
    Publication date: April 2, 2020
    Inventors: Gaurav Gupta, William J. Gallagher
  • Publication number: 20200027745
    Abstract: A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.
    Type: Application
    Filed: December 13, 2018
    Publication date: January 23, 2020
    Inventors: William J. Gallagher, Marinus Johannes Petrus Hopstaken, Ko-Tao Lee, Tomas Palacios, Daniel Piedra, Devendra K. Sadana
  • Patent number: 10541361
    Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode. The second insulating cover layer has an oxygen getter property.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chwen Yu, Shy-Jay Lin, William J. Gallagher
  • Publication number: 20200005845
    Abstract: In some embodiments, the present application provides a magnetic memory device. The magnetic memory device comprises a bottom electrode, and a first synthetic anti-ferromagnetic (SyAF) layer including a first pinning layer and a second pinning layer disposed over the bottom electrode and having opposite magnetization directions and separated by a first spacer layer. The magnetic memory device further comprises a reference layer disposed over the first pair of pinning layers and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further comprises a second synthetic anti-ferromagnetic (SyAF) layer including a third pinning layer and a fourth pinning layer disposed over the free layer and having opposite magnetization directions and separated by a second spacer layer.
    Type: Application
    Filed: April 26, 2019
    Publication date: January 2, 2020
    Inventors: Gaurav Gupta, Zhiqiang Wu, William J. Gallagher
  • Patent number: 10452363
    Abstract: Techniques and mechanisms for conversion of code of a first type to bytecode. Apex provides various unique characteristics. When converting to bytecode, these characteristics are handled to provide bytecode functionality. Some of the unique characteristics of Apex include Autoboxing, SOQL, Properties, Comparisons, Modifiers, Code coverage mechanisms and Sharing mechanisms.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: October 22, 2019
    Assignee: salesforce.com, inc.
    Inventors: Gregory D. Fee, William J. Gallagher
  • Publication number: 20190165260
    Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode. The second insulating cover layer has an oxygen getter property.
    Type: Application
    Filed: March 29, 2018
    Publication date: May 30, 2019
    Inventors: Chwen Yu, Shy-Jay Lin, William J. Gallagher
  • Patent number: 10276227
    Abstract: A method for verifying a write operation in a memory cell (e.g., a non-volatile memory cell) that includes performing a first read operation of the memory cell to measure a first current associated with the memory cell and comparing the measured first current associated with the memory cell to a first predetermined threshold current to determine whether the write operation changed the state of the memory cell. If the measured first current associated with the memory cell indicates the write operation did change the state of the memory cell the method further includes performing a second read operation of the memory cell to measure a second current associated with the memory cell and comparing the measured second current associated with the memory cell to a second predetermined threshold current to determine whether the write operation changed the state of the memory cell to the desired state or an intermediate state.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chien-Ye Lee, Jenn-Jou Wu, Yi-Chieh Chiu, Yi-Chun Shih, William J. Gallagher
  • Patent number: 10217641
    Abstract: A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: February 26, 2019
    Assignees: International Business Machines Corporation, MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: William J. Gallagher, Marinus Johannes Petrus Hopstaken, Ko-Tao Lee, Tomas Palacios, Daniel Piedra, Devendra K. Sadana
  • Publication number: 20180315464
    Abstract: A method for verifying a write operation in a memory cell (e.g., a non-volatile memory cell) that includes performing a first read operation of the memory cell to measure a first current associated with the memory cell and comparing the measured first current associated with the memory cell to a first predetermined threshold current to determine whether the write operation changed the state of the memory cell. If the measured first current associated with the memory cell indicates the write operation did change the state of the memory cell the method further includes performing a second read operation of the memory cell to measure a second current associated with the memory cell and comparing the measured second current associated with the memory cell to a second predetermined threshold current to determine whether the write operation changed the state of the memory cell to the desired state or an intermediate state.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Inventors: Yu-Der Chih, Chien-Ye Lee, Jenn-Jou Wu, Yi-Chieh Chiu, Yi-Chun Shih, William J. Gallagher
  • Patent number: 10043607
    Abstract: Present disclosure relates to magnetic materials, chips having magnetic materials, and methods of forming magnetic materials. In certain embodiments, magnetic materials may include a seed layer, and a cobalt-based alloy formed on seed layer. The seed layer may include copper, cobalt, nickel, platinum, palladium, ruthenium, iron, nickel alloy, cobalt-iron-boron alloy, nickel-iron alloy, and any combination of these materials. In certain embodiments, the chip may include one or more on-chip magnetic structures. Each on-chip magnetic structure may include a seed layer, and a cobalt-based alloy formed on seed layer. In certain embodiments, method may include: placing a seed layer in an aqueous electroless plating bath to form a cobalt-based alloy on seed layer. In certain embodiments, the aqueous electroless plating bath may include sodium tetraborate, an alkali metal tartrate, ammonium sulfate, cobalt sulfate, ferric ammonium sulfate and sodium borohydride and has a pH between about 9 to about 13.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Yu Luo, Lubomyr T. Romankiw, Joonah Yoon