Abstract: A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO2, where X is a metal.

Abstract: A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO2, where X is a metal.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).

Abstract: A multi-state non-volatile ferroelectric memory includes a field effect transistor having a gate insulator formed of ferroelectric material. The ferroelectric material is separated into regions of different characteristics, e.g. different thicknesses, different coercive field values, etc., so as to provide a plurality of different threshold voltages for the field effect transistor.

Abstract: A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an on-state. The ferroelectric transistor (32) functions as a nonvolatile latch and pass device to provide the electrical interconnect path that links multiple Configurable Logic Blocks (CLBs). The programming transistor (34) is selected to transfer a depolarizing voltage to the gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an off-state.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (13) of ferroelectric material disposed on a semiconductor substrate (11) and a gate electrode (17) formed on a portion (26) of the layer (13) of ferroelectric material. The portion (26) of the layer (13) of ferroelectric material sandwiched between a semiconductor substrate (11) and a gate electrode (17) retains its ferroelectric activity. The portions (21, 22) of the layer (13) of ferroelectric material adjacent the portion (26) are damaged and thereby rendered ferroelectrically inactive. A source contact (31) and a drain contact (32) are formed through the damaged portions (21, 22) of the layer (13) of ferroelectric material.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (15) of ferroelectric material disposed on a semiconductor substrate (11) and a gate structure (27) formed on the semiconductor substrate (11). A source region (23) and a drain region (24) are formed on the semiconductor substrate such that the source region (23) and the drain region (24) are laterally spaced apart from the gate structure (27).

Abstract: Ferroelectric transistors are combined with MOSFETs to perform logic functions. The logic functions include a non-volatile ferroelectric latch (30), a clocked non-volatile ferroelectric latch (50), a programmable switch (60), an edge-triggered complementary flip-flop (78), a tri-state logic circuit (80), a ferroelectric logic NAND-gate (100), a clocked ferroelectric logic NAND-gate (140), and a programmable logic function (150). The programmable logic function (150) includes a programming terminal (156) to select between a NOR-gate function and a NAND-gate function.

Abstract: A layered bismuth ferroelectric structure (12) and a method for forming the bismuth layered ferroelectric structure (12). A monolayer (12A) of bismuth is formed in intimate contact with a single crystalline semiconductor material (11). A layered ferroelectric material (12) is grown on the monolayer (12A) of bismuth such that the monolayer (12A) of bismuth becomes a part of the layered ferroelectric material (12). The ferroelectric material (12) forms a layered ferroelectric material which is not a pure perovskite, wherein the crystalline structure at the interface between the single crystalline semiconductor material (11) and the monolayer (12A) of bismuth are substantially the same.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (13) of ferroelectric material disposed on a semiconductor substrate (11) and a gate electrode (17) formed on a portion (26) of the layer (13) of ferroelectric material. The portion (26) of the layer (13) of ferroelectric material sandwiched between a semiconductor substrate (11) and a gate electrode (17) retains its ferroelectric activity. The portions (21, 22) of the layer (13) of ferroelectric material adjacent the portion (26) are damaged and thereby rendered ferroelectrically inactive. A source contact (31) and a drain contact (32) are formed through the damaged portions (21, 22) of the layer (13) of ferroelectric material.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (15) of ferroelectric material disposed on a semiconductor substrate (11) and a gate structure (27) formed on the semiconductor substrate (11). A source region (23) and a drain region (24) are formed on the semiconductor substrate such that the source region (23) and the drain region (24) are laterally spaced apart from the gate structure (27).

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).

Abstract: A layered bismuth ferroelectric structure (12) and a method for forming the bismuth layered ferroelectric structure (12). A monolayer (12A) of bismuth is formed in intimate contact with a single crystalline semiconductor material (11). A layered ferroelectric material (12) is grown on the monolayer (12A) of bismuth such that the monolayer (12A) of bismuth becomes a part of the layered ferroelectric material (12). The ferroelectric material (12) forms a layered ferroelectric material which is not a pure perovskite, wherein the crystalline structure at the interface between the single crystalline semiconductor material (11) and the monolayer (12A) of bismuth are substantially the same.

Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

Abstract: A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).

Abstract: The present invention encompasses a complementary semiconductor device having the same type of material providing the ohmic contacts (117, 119) to both the N-type and P-type devices. In a preferred embodiment, P-source and P -drain regions ( 80, 82 ) are heavily doped with a P-type impurity (81, 83) so that an ohmic with N-type impurity can be used as an ohmic contact. One ohmic material that may be used is nickel-germanium-tungsten. Nickel-germanium-tungsten is etchable, and therefore does not require lift-off processing. Furthermore, a preferred complementary semiconductor device made in accordance with the present invention is compatible with modern aluminum based VLSI interconnection processes.

Abstract: A circuit derives all power from a single clock input terminal and has no connections to separate power source or power sink terminals. The circuit configuration is applicable to many functions such as inverters, logic gates (NAND, NOR, etc.), and storage elements. When connected to form an inverter function, a current electrode of a first transistor is coupled to the clock input terminal and a control electrode is coupled to a signal input terminal while a second transistor has a current electrode coupled to the clock input terminal and a control electrode coupled the signal input terminal. Both transistors have a second current electrode coupled to an output of the inverter.

Abstract: A circuit derives all power from a single clock input terminal and has no connections to separate power source or power sink terminals. The circuit configuration is applicable to many functions such as inverters, logic gates (NAND, NOR, etc.), and storage elements. When connected to form an inverter function, a current electrode of a first transistor is coupled to the clock input terminal and a control electrode is coupled to a signal input terminal while a second transistor has a current electrode coupled to the clock input terminal and a control electrode coupled the signal input terminal. Both transistors have a second current electrode coupled to an output of the inverter.

Abstract: Logic circuits using a heterojunction field effect transistor structure having vertically stacked complementary devices is provided. A P-channel quantum well and an N-channel quantum well are formed near each other under a single gate electrode and separated from each other by a thin layer of barrier material. P-source and P-drain regions couple to the P-channel. N-source and N-drain regions couple to the N-channel. The P-source/drain regions are electrically isolated from the N-source/drain regions so the P-channel and N-channel devices may be interconnected to provide many logic functions.

Abstract: A heterojunction field effect transistor structure having a plurality of vertically stacked field effect devices. Two or more devices having electrically independent source and drain regions are formed such that a single gate electrode controls current flow in each of the devices. Each of the vertically stacked FETs have electrically isolated channel regions which may be controlled by a single gate electrode. Vertically stacked devices provide greater device packing density.